1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <arch.h> 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu #include <common/bl_common.h> 12*91f16700Schasinglulu #include <common/debug.h> 13*91f16700Schasinglulu #include <lib/mmio.h> 14*91f16700Schasinglulu #include <lib/xlat_tables/xlat_mmu_helpers.h> 15*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables_defs.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu #include <rpi_shared.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* Data structure which holds the extents of the trusted SRAM for BL1 */ 20*91f16700Schasinglulu static meminfo_t bl1_tzram_layout; 21*91f16700Schasinglulu 22*91f16700Schasinglulu meminfo_t *bl1_plat_sec_mem_layout(void) 23*91f16700Schasinglulu { 24*91f16700Schasinglulu return &bl1_tzram_layout; 25*91f16700Schasinglulu } 26*91f16700Schasinglulu 27*91f16700Schasinglulu /******************************************************************************* 28*91f16700Schasinglulu * Perform any BL1 specific platform actions. 29*91f16700Schasinglulu ******************************************************************************/ 30*91f16700Schasinglulu void bl1_early_platform_setup(void) 31*91f16700Schasinglulu { 32*91f16700Schasinglulu /* use the 19.2 MHz clock for the architected timer */ 33*91f16700Schasinglulu mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_CONTROL_OFFSET, 0); 34*91f16700Schasinglulu mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_PRESCALER_OFFSET, 35*91f16700Schasinglulu 0x80000000); 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* Initialize the console to provide early debug support */ 38*91f16700Schasinglulu rpi3_console_init(); 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* Allow BL1 to see the whole Trusted RAM */ 41*91f16700Schasinglulu bl1_tzram_layout.total_base = BL_RAM_BASE; 42*91f16700Schasinglulu bl1_tzram_layout.total_size = BL_RAM_SIZE; 43*91f16700Schasinglulu } 44*91f16700Schasinglulu 45*91f16700Schasinglulu /****************************************************************************** 46*91f16700Schasinglulu * Perform the very early platform specific architecture setup. This only 47*91f16700Schasinglulu * does basic initialization. Later architectural setup (bl1_arch_setup()) 48*91f16700Schasinglulu * does not do anything platform specific. 49*91f16700Schasinglulu *****************************************************************************/ 50*91f16700Schasinglulu void bl1_plat_arch_setup(void) 51*91f16700Schasinglulu { 52*91f16700Schasinglulu rpi3_setup_page_tables(bl1_tzram_layout.total_base, 53*91f16700Schasinglulu bl1_tzram_layout.total_size, 54*91f16700Schasinglulu BL_CODE_BASE, BL1_CODE_END, 55*91f16700Schasinglulu BL1_RO_DATA_BASE, BL1_RO_DATA_END 56*91f16700Schasinglulu #if USE_COHERENT_MEM 57*91f16700Schasinglulu , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END 58*91f16700Schasinglulu #endif 59*91f16700Schasinglulu ); 60*91f16700Schasinglulu 61*91f16700Schasinglulu enable_mmu_el3(0); 62*91f16700Schasinglulu } 63*91f16700Schasinglulu 64*91f16700Schasinglulu void bl1_platform_setup(void) 65*91f16700Schasinglulu { 66*91f16700Schasinglulu uint32_t __unused rev; 67*91f16700Schasinglulu int __unused rc; 68*91f16700Schasinglulu 69*91f16700Schasinglulu rc = rpi3_vc_hardware_get_board_revision(&rev); 70*91f16700Schasinglulu 71*91f16700Schasinglulu if (rc == 0) { 72*91f16700Schasinglulu const char __unused *model, __unused *info; 73*91f16700Schasinglulu 74*91f16700Schasinglulu switch (rev) { 75*91f16700Schasinglulu case 0xA02082: 76*91f16700Schasinglulu model = "Raspberry Pi 3 Model B"; 77*91f16700Schasinglulu info = "(1GB, Sony, UK)"; 78*91f16700Schasinglulu break; 79*91f16700Schasinglulu case 0xA22082: 80*91f16700Schasinglulu model = "Raspberry Pi 3 Model B"; 81*91f16700Schasinglulu info = "(1GB, Embest, China)"; 82*91f16700Schasinglulu break; 83*91f16700Schasinglulu case 0xA020D3: 84*91f16700Schasinglulu model = "Raspberry Pi 3 Model B+"; 85*91f16700Schasinglulu info = "(1GB, Sony, UK)"; 86*91f16700Schasinglulu break; 87*91f16700Schasinglulu default: 88*91f16700Schasinglulu model = "Unknown"; 89*91f16700Schasinglulu info = "(Unknown)"; 90*91f16700Schasinglulu ERROR("rpi3: Unknown board revision 0x%08x\n", rev); 91*91f16700Schasinglulu break; 92*91f16700Schasinglulu } 93*91f16700Schasinglulu 94*91f16700Schasinglulu NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev); 95*91f16700Schasinglulu } else { 96*91f16700Schasinglulu ERROR("rpi3: Unable to detect board revision\n"); 97*91f16700Schasinglulu } 98*91f16700Schasinglulu 99*91f16700Schasinglulu /* Initialise the IO layer and register platform IO devices */ 100*91f16700Schasinglulu plat_rpi3_io_setup(); 101*91f16700Schasinglulu } 102