1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef RK3399_DEF_H 8*91f16700Schasinglulu #define RK3399_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <addressmap.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define RK3399_PRIMARY_CPU 0x0 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15*91f16700Schasinglulu #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16*91f16700Schasinglulu 17*91f16700Schasinglulu /************************************************************************** 18*91f16700Schasinglulu * UART related constants 19*91f16700Schasinglulu **************************************************************************/ 20*91f16700Schasinglulu #define RK3399_BAUDRATE 115200 21*91f16700Schasinglulu #define RK3399_UART_CLOCK 24000000 22*91f16700Schasinglulu 23*91f16700Schasinglulu /****************************************************************************** 24*91f16700Schasinglulu * System counter frequency related constants 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu #define SYS_COUNTER_FREQ_IN_TICKS 24000000 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* Base rockchip_platform compatible GIC memory map */ 29*91f16700Schasinglulu #define BASE_GICD_BASE (GIC500_BASE) 30*91f16700Schasinglulu #define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) 31*91f16700Schasinglulu 32*91f16700Schasinglulu /***************************************************************************** 33*91f16700Schasinglulu * CCI-400 related constants 34*91f16700Schasinglulu ******************************************************************************/ 35*91f16700Schasinglulu #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 36*91f16700Schasinglulu #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 37*91f16700Schasinglulu 38*91f16700Schasinglulu /****************************************************************************** 39*91f16700Schasinglulu * sgi, ppi 40*91f16700Schasinglulu ******************************************************************************/ 41*91f16700Schasinglulu #define ARM_IRQ_SEC_PHY_TIMER 29 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_0 8 44*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_1 9 45*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_2 10 46*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_3 11 47*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_4 12 48*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_5 13 49*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_6 14 50*91f16700Schasinglulu #define ARM_IRQ_SEC_SGI_7 15 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* 53*91f16700Schasinglulu * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 54*91f16700Schasinglulu * terminology. On a GICv2 system or mode, the lists will be merged and treated 55*91f16700Schasinglulu * as Group 0 interrupts. 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu #define PLAT_RK_GICV3_G1S_IRQS \ 58*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 59*91f16700Schasinglulu INTR_GROUP1S, GIC_INTR_CFG_LEVEL) 60*91f16700Schasinglulu 61*91f16700Schasinglulu #define PLAT_RK_GICV3_G0_IRQS \ 62*91f16700Schasinglulu INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 63*91f16700Schasinglulu INTR_GROUP0, GIC_INTR_CFG_LEVEL) 64*91f16700Schasinglulu 65*91f16700Schasinglulu #endif /* RK3399_DEF_H */ 66