1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <common/runtime_svc.h> 9*91f16700Schasinglulu #include <lib/mmio.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <cdn_dp.h> 12*91f16700Schasinglulu #include <dfs.h> 13*91f16700Schasinglulu #include <plat_sip_calls.h> 14*91f16700Schasinglulu #include <rockchip_sip_svc.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define RK_SIP_DDR_CFG 0x82000008 17*91f16700Schasinglulu #define DRAM_INIT 0x00 18*91f16700Schasinglulu #define DRAM_SET_RATE 0x01 19*91f16700Schasinglulu #define DRAM_ROUND_RATE 0x02 20*91f16700Schasinglulu #define DRAM_SET_AT_SR 0x03 21*91f16700Schasinglulu #define DRAM_GET_BW 0x04 22*91f16700Schasinglulu #define DRAM_GET_RATE 0x05 23*91f16700Schasinglulu #define DRAM_CLR_IRQ 0x06 24*91f16700Schasinglulu #define DRAM_SET_PARAM 0x07 25*91f16700Schasinglulu #define DRAM_SET_ODT_PD 0x08 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define RK_SIP_HDCP_CONTROL 0x82000009 28*91f16700Schasinglulu #define RK_SIP_HDCP_KEY_DATA64 0xC200000A 29*91f16700Schasinglulu 30*91f16700Schasinglulu uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, 31*91f16700Schasinglulu uint64_t id, uint64_t arg2) 32*91f16700Schasinglulu { 33*91f16700Schasinglulu switch (id) { 34*91f16700Schasinglulu case DRAM_SET_RATE: 35*91f16700Schasinglulu return ddr_set_rate((uint32_t)arg0); 36*91f16700Schasinglulu case DRAM_ROUND_RATE: 37*91f16700Schasinglulu return ddr_round_rate((uint32_t)arg0); 38*91f16700Schasinglulu case DRAM_GET_RATE: 39*91f16700Schasinglulu return ddr_get_rate(); 40*91f16700Schasinglulu case DRAM_SET_ODT_PD: 41*91f16700Schasinglulu dram_set_odt_pd(arg0, arg1, arg2); 42*91f16700Schasinglulu break; 43*91f16700Schasinglulu default: 44*91f16700Schasinglulu break; 45*91f16700Schasinglulu } 46*91f16700Schasinglulu 47*91f16700Schasinglulu return 0; 48*91f16700Schasinglulu } 49*91f16700Schasinglulu 50*91f16700Schasinglulu uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid, 51*91f16700Schasinglulu u_register_t x1, 52*91f16700Schasinglulu u_register_t x2, 53*91f16700Schasinglulu u_register_t x3, 54*91f16700Schasinglulu u_register_t x4, 55*91f16700Schasinglulu void *cookie, 56*91f16700Schasinglulu void *handle, 57*91f16700Schasinglulu u_register_t flags) 58*91f16700Schasinglulu { 59*91f16700Schasinglulu #ifdef PLAT_RK_DP_HDCP 60*91f16700Schasinglulu uint64_t x5, x6; 61*91f16700Schasinglulu #endif 62*91f16700Schasinglulu 63*91f16700Schasinglulu switch (smc_fid) { 64*91f16700Schasinglulu case RK_SIP_DDR_CFG: 65*91f16700Schasinglulu SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4)); 66*91f16700Schasinglulu #ifdef PLAT_RK_DP_HDCP 67*91f16700Schasinglulu case RK_SIP_HDCP_CONTROL: 68*91f16700Schasinglulu SMC_RET1(handle, dp_hdcp_ctrl(x1)); 69*91f16700Schasinglulu case RK_SIP_HDCP_KEY_DATA64: 70*91f16700Schasinglulu x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); 71*91f16700Schasinglulu x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6); 72*91f16700Schasinglulu SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6)); 73*91f16700Schasinglulu #endif 74*91f16700Schasinglulu default: 75*91f16700Schasinglulu ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 76*91f16700Schasinglulu SMC_RET1(handle, SMC_UNK); 77*91f16700Schasinglulu } 78*91f16700Schasinglulu } 79