1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <lib/utils_def.h> 12*91f16700Schasinglulu #include <plat/common/common_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <bl31_param.h> 15*91f16700Schasinglulu #include <rk3399_def.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * Platform binary types for linking 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 21*91f16700Schasinglulu #define PLATFORM_LINKER_ARCH aarch64 22*91f16700Schasinglulu 23*91f16700Schasinglulu /******************************************************************************* 24*91f16700Schasinglulu * Generic platform constants 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* Size of cacheable stacks */ 28*91f16700Schasinglulu #if defined(IMAGE_BL1) 29*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x440 30*91f16700Schasinglulu #elif defined(IMAGE_BL2) 31*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x400 32*91f16700Schasinglulu #elif defined(IMAGE_BL31) 33*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x800 34*91f16700Schasinglulu #elif defined(IMAGE_BL32) 35*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x440 36*91f16700Schasinglulu #endif 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 39*91f16700Schasinglulu 40*91f16700Schasinglulu #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 41*91f16700Schasinglulu #define PLATFORM_SYSTEM_COUNT U(1) 42*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(2) 43*91f16700Schasinglulu #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 44*91f16700Schasinglulu #define PLATFORM_CLUSTER1_CORE_COUNT U(2) 45*91f16700Schasinglulu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 46*91f16700Schasinglulu PLATFORM_CLUSTER0_CORE_COUNT) 47*91f16700Schasinglulu #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 48*91f16700Schasinglulu #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 49*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT + \ 50*91f16700Schasinglulu PLATFORM_CORE_COUNT) 51*91f16700Schasinglulu #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 52*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* 55*91f16700Schasinglulu * This macro defines the deepest retention state possible. A higher state 56*91f16700Schasinglulu * id will represent an invalid or a power down state. 57*91f16700Schasinglulu */ 58*91f16700Schasinglulu #define PLAT_MAX_RET_STATE U(1) 59*91f16700Schasinglulu 60*91f16700Schasinglulu /* 61*91f16700Schasinglulu * This macro defines the deepest power down states possible. Any state ID 62*91f16700Schasinglulu * higher than this is invalid. 63*91f16700Schasinglulu */ 64*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE U(2) 65*91f16700Schasinglulu 66*91f16700Schasinglulu /******************************************************************************* 67*91f16700Schasinglulu * Platform specific page table and MMU setup constants 68*91f16700Schasinglulu ******************************************************************************/ 69*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 70*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 71*91f16700Schasinglulu #define MAX_XLAT_TABLES 20 72*91f16700Schasinglulu #define MAX_MMAP_REGIONS 25 73*91f16700Schasinglulu 74*91f16700Schasinglulu /******************************************************************************* 75*91f16700Schasinglulu * Declarations and constants to access the mailboxes safely. Each mailbox is 76*91f16700Schasinglulu * aligned on the biggest cache line size in the platform. This is known only 77*91f16700Schasinglulu * to the platform as it might have a combination of integrated and external 78*91f16700Schasinglulu * caches. Such alignment ensures that two maiboxes do not sit on the same cache 79*91f16700Schasinglulu * line at any cache level. They could belong to different cpus/clusters & 80*91f16700Schasinglulu * get written while being protected by different locks causing corruption of 81*91f16700Schasinglulu * a valid mailbox address. 82*91f16700Schasinglulu ******************************************************************************/ 83*91f16700Schasinglulu #define CACHE_WRITEBACK_SHIFT 6 84*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* 87*91f16700Schasinglulu * Define GICD and GICC and GICR base 88*91f16700Schasinglulu */ 89*91f16700Schasinglulu #define PLAT_RK_GICD_BASE BASE_GICD_BASE 90*91f16700Schasinglulu #define PLAT_RK_GICR_BASE BASE_GICR_BASE 91*91f16700Schasinglulu #define PLAT_RK_GICC_BASE 0 92*91f16700Schasinglulu 93*91f16700Schasinglulu #define PLAT_RK_UART_BASE UART2_BASE 94*91f16700Schasinglulu #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK 95*91f16700Schasinglulu #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE 96*91f16700Schasinglulu 97*91f16700Schasinglulu #define PLAT_RK_CCI_BASE CCI500_BASE 98*91f16700Schasinglulu 99*91f16700Schasinglulu #define PLAT_RK_PRIMARY_CPU 0x0 100*91f16700Schasinglulu 101*91f16700Schasinglulu #define PSRAM_DO_DDR_RESUME 1 102*91f16700Schasinglulu #define PSRAM_CHECK_WAKEUP_CPU 0 103*91f16700Schasinglulu 104*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 105