1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <m0_param.h> 8*91f16700Schasinglulu 9*91f16700SchasingluluOUTPUT_FORMAT("elf32-littlearm") 10*91f16700Schasinglulu 11*91f16700SchasingluluSECTIONS { 12*91f16700Schasinglulu .m0_bin 0 : { 13*91f16700Schasinglulu KEEP(*(.isr_vector)) 14*91f16700Schasinglulu ASSERT(. == 0xc0, "ISR vector has the wrong size."); 15*91f16700Schasinglulu ASSERT(. == PARAM_ADDR, "M0 params should go right behind ISR table."); 16*91f16700Schasinglulu . += PARAM_M0_SIZE; 17*91f16700Schasinglulu *(.text*) 18*91f16700Schasinglulu *(.rodata*) 19*91f16700Schasinglulu *(.data*) 20*91f16700Schasinglulu *(.bss*) 21*91f16700Schasinglulu . = ALIGN(8); 22*91f16700Schasinglulu *(.co_stack*) 23*91f16700Schasinglulu } 24*91f16700Schasinglulu 25*91f16700Schasinglulu /DISCARD/ : { *(.comment) *(.note*) } 26*91f16700Schasinglulu} 27