1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <dram_regs.h> 8*91f16700Schasinglulu #include <m0_param.h> 9*91f16700Schasinglulu #include <pmu_bits.h> 10*91f16700Schasinglulu #include <pmu_regs.h> 11*91f16700Schasinglulu #include "misc_regs.h" 12*91f16700Schasinglulu #include "rk3399_mcu.h" 13*91f16700Schasinglulu 14*91f16700Schasinglulu static uint32_t gatedis_con0; 15*91f16700Schasinglulu 16*91f16700Schasinglulu static void idle_port(void) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); 19*91f16700Schasinglulu mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); 20*91f16700Schasinglulu 21*91f16700Schasinglulu mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 22*91f16700Schasinglulu (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 23*91f16700Schasinglulu while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 24*91f16700Schasinglulu ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) != 25*91f16700Schasinglulu ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 26*91f16700Schasinglulu continue; 27*91f16700Schasinglulu } 28*91f16700Schasinglulu 29*91f16700Schasinglulu static void deidle_port(void) 30*91f16700Schasinglulu { 31*91f16700Schasinglulu mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 32*91f16700Schasinglulu (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 33*91f16700Schasinglulu while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 34*91f16700Schasinglulu ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 35*91f16700Schasinglulu continue; 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ 38*91f16700Schasinglulu mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); 39*91f16700Schasinglulu } 40*91f16700Schasinglulu 41*91f16700Schasinglulu static void ddr_set_pll(void) 42*91f16700Schasinglulu { 43*91f16700Schasinglulu mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); 44*91f16700Schasinglulu 45*91f16700Schasinglulu mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); 46*91f16700Schasinglulu mmio_write_32(CRU_BASE + CRU_DPLL_CON0, 47*91f16700Schasinglulu mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); 48*91f16700Schasinglulu mmio_write_32(CRU_BASE + CRU_DPLL_CON1, 49*91f16700Schasinglulu mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); 50*91f16700Schasinglulu mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); 51*91f16700Schasinglulu 52*91f16700Schasinglulu while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) 53*91f16700Schasinglulu continue; 54*91f16700Schasinglulu 55*91f16700Schasinglulu mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); 56*91f16700Schasinglulu } 57*91f16700Schasinglulu 58*91f16700Schasinglulu __attribute__((noreturn)) void m0_main(void) 59*91f16700Schasinglulu { 60*91f16700Schasinglulu mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); 61*91f16700Schasinglulu mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); 62*91f16700Schasinglulu idle_port(); 63*91f16700Schasinglulu 64*91f16700Schasinglulu mmio_write_32(CIC_BASE + CIC_CTRL0, 65*91f16700Schasinglulu (((0x3 << 4) | (1 << 2) | 1) << 16) | 66*91f16700Schasinglulu (1 << 2) | 1 | 67*91f16700Schasinglulu mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); 68*91f16700Schasinglulu while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) 69*91f16700Schasinglulu continue; 70*91f16700Schasinglulu 71*91f16700Schasinglulu ddr_set_pll(); 72*91f16700Schasinglulu mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); 73*91f16700Schasinglulu while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) 74*91f16700Schasinglulu continue; 75*91f16700Schasinglulu 76*91f16700Schasinglulu deidle_port(); 77*91f16700Schasinglulu mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); 78*91f16700Schasinglulu mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); 79*91f16700Schasinglulu 80*91f16700Schasinglulu mmio_write_32(PARAM_ADDR + PARAM_M0_DONE, M0_DONE_FLAG); 81*91f16700Schasinglulu 82*91f16700Schasinglulu for (;;) 83*91f16700Schasinglulu __asm__ volatile ("wfi"); 84*91f16700Schasinglulu } 85