1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <dram.h> 8*91f16700Schasinglulu #include <plat_private.h> 9*91f16700Schasinglulu #include <rk3399_def.h> 10*91f16700Schasinglulu #include <secure.h> 11*91f16700Schasinglulu #include <soc.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu __pmusramdata struct rk3399_sdram_params sdram_config; 14*91f16700Schasinglulu 15*91f16700Schasinglulu void dram_init(void) 16*91f16700Schasinglulu { 17*91f16700Schasinglulu uint32_t os_reg2_val, i; 18*91f16700Schasinglulu 19*91f16700Schasinglulu os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); 20*91f16700Schasinglulu sdram_config.dramtype = SYS_REG_DEC_DDRTYPE(os_reg2_val); 21*91f16700Schasinglulu sdram_config.num_channels = SYS_REG_DEC_NUM_CH(os_reg2_val); 22*91f16700Schasinglulu sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >> 23*91f16700Schasinglulu 10) & 0x1f; 24*91f16700Schasinglulu 25*91f16700Schasinglulu for (i = 0; i < 2; i++) { 26*91f16700Schasinglulu struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; 27*91f16700Schasinglulu struct rk3399_msch_timings *noc = &ch->noc_timings; 28*91f16700Schasinglulu 29*91f16700Schasinglulu if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i))) 30*91f16700Schasinglulu continue; 31*91f16700Schasinglulu 32*91f16700Schasinglulu ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); 33*91f16700Schasinglulu ch->col = SYS_REG_DEC_COL(os_reg2_val, i); 34*91f16700Schasinglulu ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); 35*91f16700Schasinglulu ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); 36*91f16700Schasinglulu ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); 37*91f16700Schasinglulu ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); 38*91f16700Schasinglulu ch->cs0_row = SYS_REG_DEC_CS0_ROW(os_reg2_val, i); 39*91f16700Schasinglulu ch->cs1_row = SYS_REG_DEC_CS1_ROW(os_reg2_val, i); 40*91f16700Schasinglulu ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF); 41*91f16700Schasinglulu 42*91f16700Schasinglulu noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) + 43*91f16700Schasinglulu MSCH_DDRTIMINGA0); 44*91f16700Schasinglulu noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) + 45*91f16700Schasinglulu MSCH_DDRTIMINGB0); 46*91f16700Schasinglulu noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) + 47*91f16700Schasinglulu MSCH_DDRTIMINGC0); 48*91f16700Schasinglulu noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) + 49*91f16700Schasinglulu MSCH_DEVTODEV0); 50*91f16700Schasinglulu noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE); 51*91f16700Schasinglulu noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0); 52*91f16700Schasinglulu } 53*91f16700Schasinglulu } 54