1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef DFS_H 8*91f16700Schasinglulu #define DFS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu struct rk3399_sdram_default_config { 13*91f16700Schasinglulu unsigned char bl; 14*91f16700Schasinglulu /* 1:auto precharge, 0:never auto precharge */ 15*91f16700Schasinglulu unsigned char ap; 16*91f16700Schasinglulu /* dram driver strength */ 17*91f16700Schasinglulu unsigned char dramds; 18*91f16700Schasinglulu /* dram ODT, if odt=0, this parameter invalid */ 19*91f16700Schasinglulu unsigned char dramodt; 20*91f16700Schasinglulu /* ca ODT, if odt=0, this parameter invalid 21*91f16700Schasinglulu * only used by LPDDR4 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu unsigned char caodt; 24*91f16700Schasinglulu unsigned char burst_ref_cnt; 25*91f16700Schasinglulu /* zqcs period, unit(s) */ 26*91f16700Schasinglulu unsigned char zqcsi; 27*91f16700Schasinglulu }; 28*91f16700Schasinglulu 29*91f16700Schasinglulu struct drv_odt_lp_config { 30*91f16700Schasinglulu uint32_t pd_idle; 31*91f16700Schasinglulu uint32_t sr_idle; 32*91f16700Schasinglulu uint32_t sr_mc_gate_idle; 33*91f16700Schasinglulu uint32_t srpd_lite_idle; 34*91f16700Schasinglulu uint32_t standby_idle; 35*91f16700Schasinglulu uint32_t odt_en; 36*91f16700Schasinglulu 37*91f16700Schasinglulu uint32_t dram_side_drv; 38*91f16700Schasinglulu uint32_t dram_side_dq_odt; 39*91f16700Schasinglulu uint32_t dram_side_ca_odt; 40*91f16700Schasinglulu }; 41*91f16700Schasinglulu 42*91f16700Schasinglulu uint32_t ddr_set_rate(uint32_t hz); 43*91f16700Schasinglulu uint32_t ddr_round_rate(uint32_t hz); 44*91f16700Schasinglulu uint32_t ddr_get_rate(void); 45*91f16700Schasinglulu uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2); 46*91f16700Schasinglulu void dram_dfs_init(void); 47*91f16700Schasinglulu void ddr_prepare_for_sys_suspend(void); 48*91f16700Schasinglulu void ddr_prepare_for_sys_resume(void); 49*91f16700Schasinglulu 50*91f16700Schasinglulu #endif /* DFS_H */ 51