1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef RK3368_DEF_H 8*91f16700Schasinglulu #define RK3368_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Special value used to verify platform parameters from BL2 to BL3-1 */ 11*91f16700Schasinglulu #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define CCI400_BASE 0xffb90000 14*91f16700Schasinglulu #define CCI400_SIZE 0x10000 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define GIC400_BASE 0xffb70000 17*91f16700Schasinglulu #define GIC400_SIZE 0x10000 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define STIME_BASE 0xff830000 20*91f16700Schasinglulu #define STIME_SIZE 0x10000 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define CRU_BASE 0xff760000 23*91f16700Schasinglulu #define CRU_SIZE 0x10000 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define GRF_BASE 0xff770000 26*91f16700Schasinglulu #define GRF_SIZE 0x10000 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define SGRF_BASE 0xff740000 29*91f16700Schasinglulu #define SGRF_SIZE 0x10000 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define PMU_BASE 0xff730000 32*91f16700Schasinglulu #define PMU_GRF_BASE 0xff738000 33*91f16700Schasinglulu #define PMU_SIZE 0x10000 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define RK_INTMEM_BASE 0xff8c0000 36*91f16700Schasinglulu #define RK_INTMEM_SIZE 0x10000 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define UART0_BASE 0xff180000 39*91f16700Schasinglulu #define UART0_SIZE 0x10000 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define UART1_BASE 0xff190000 42*91f16700Schasinglulu #define UART1_SIZE 0x10000 43*91f16700Schasinglulu 44*91f16700Schasinglulu #define UART2_BASE 0xff690000 45*91f16700Schasinglulu #define UART2_SIZE 0x10000 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define UART3_BASE 0xff1b0000 48*91f16700Schasinglulu #define UART3_SIZE 0x10000 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define UART4_BASE 0xff1c0000 51*91f16700Schasinglulu #define UART4_SIZE 0x10000 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define CRU_BASE 0xff760000 54*91f16700Schasinglulu 55*91f16700Schasinglulu #define PMUSRAM_BASE 0xff720000 56*91f16700Schasinglulu #define PMUSRAM_SIZE 0x10000 57*91f16700Schasinglulu #define PMUSRAM_RSIZE 0x1000 58*91f16700Schasinglulu 59*91f16700Schasinglulu #define DDR_PCTL_BASE 0xff610000 60*91f16700Schasinglulu #define DDR_PCTL_SIZE 0x10000 61*91f16700Schasinglulu 62*91f16700Schasinglulu #define DDR_PHY_BASE 0xff620000 63*91f16700Schasinglulu #define DDR_PHY_SIZE 0x10000 64*91f16700Schasinglulu 65*91f16700Schasinglulu #define SERVICE_BUS_BASE 0xffac0000 66*91f16700Schasinglulu #define SERVICE_BUS_SISE 0x50000 67*91f16700Schasinglulu 68*91f16700Schasinglulu #define COLD_BOOT_BASE 0xffff0000 69*91f16700Schasinglulu /************************************************************************** 70*91f16700Schasinglulu * UART related constants 71*91f16700Schasinglulu **************************************************************************/ 72*91f16700Schasinglulu #define RK3368_BAUDRATE 115200 73*91f16700Schasinglulu #define RK3368_UART_CLOCK 24000000 74*91f16700Schasinglulu 75*91f16700Schasinglulu /****************************************************************************** 76*91f16700Schasinglulu * System counter frequency related constants 77*91f16700Schasinglulu ******************************************************************************/ 78*91f16700Schasinglulu #define SYS_COUNTER_FREQ_IN_TICKS 24000000 79*91f16700Schasinglulu 80*91f16700Schasinglulu /****************************************************************************** 81*91f16700Schasinglulu * GIC-400 & interrupt handling related constants 82*91f16700Schasinglulu ******************************************************************************/ 83*91f16700Schasinglulu 84*91f16700Schasinglulu /* Base rk_platform compatible GIC memory map */ 85*91f16700Schasinglulu #define RK3368_GICD_BASE (GIC400_BASE + 0x1000) 86*91f16700Schasinglulu #define RK3368_GICC_BASE (GIC400_BASE + 0x2000) 87*91f16700Schasinglulu #define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */ 88*91f16700Schasinglulu 89*91f16700Schasinglulu /***************************************************************************** 90*91f16700Schasinglulu * CCI-400 related constants 91*91f16700Schasinglulu ******************************************************************************/ 92*91f16700Schasinglulu #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3 93*91f16700Schasinglulu #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4 94*91f16700Schasinglulu 95*91f16700Schasinglulu /****************************************************************************** 96*91f16700Schasinglulu * sgi, ppi 97*91f16700Schasinglulu ******************************************************************************/ 98*91f16700Schasinglulu #define RK_IRQ_SEC_PHY_TIMER 29 99*91f16700Schasinglulu 100*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_0 8 101*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_1 9 102*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_2 10 103*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_3 11 104*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_4 12 105*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_5 13 106*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_6 14 107*91f16700Schasinglulu #define RK_IRQ_SEC_SGI_7 15 108*91f16700Schasinglulu 109*91f16700Schasinglulu /* 110*91f16700Schasinglulu * Define a list of Group 0 interrupts. 111*91f16700Schasinglulu */ 112*91f16700Schasinglulu #define PLAT_RK_GICV2_G0_IRQS \ 113*91f16700Schasinglulu INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 114*91f16700Schasinglulu GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) 115*91f16700Schasinglulu 116*91f16700Schasinglulu #endif /* RK3368_DEF_H */ 117