1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#ifndef ROCKCHIP_PLAT_LD_S 7*91f16700Schasinglulu#define ROCKCHIP_PLAT_LD_S 8*91f16700Schasinglulu 9*91f16700SchasingluluMEMORY { 10*91f16700Schasinglulu PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 11*91f16700Schasinglulu} 12*91f16700Schasinglulu 13*91f16700SchasingluluSECTIONS 14*91f16700Schasinglulu{ 15*91f16700Schasinglulu . = PMUSRAM_BASE; 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* 18*91f16700Schasinglulu * pmu_cpuson_entrypoint request address 19*91f16700Schasinglulu * align 64K when resume, so put it in the 20*91f16700Schasinglulu * start of pmusram 21*91f16700Schasinglulu */ 22*91f16700Schasinglulu .text_pmusram : { 23*91f16700Schasinglulu ASSERT(. == ALIGN(64 * 1024), 24*91f16700Schasinglulu ".pmusram.entry request 64K aligned."); 25*91f16700Schasinglulu *(.pmusram.entry) 26*91f16700Schasinglulu __bl31_pmusram_text_start = .; 27*91f16700Schasinglulu *(.pmusram.text) 28*91f16700Schasinglulu *(.pmusram.rodata) 29*91f16700Schasinglulu __bl31_pmusram_text_end = .; 30*91f16700Schasinglulu __bl31_pmusram_data_start = .; 31*91f16700Schasinglulu *(.pmusram.data) 32*91f16700Schasinglulu __bl31_pmusram_data_end = .; 33*91f16700Schasinglulu 34*91f16700Schasinglulu } >PMUSRAM 35*91f16700Schasinglulu} 36*91f16700Schasinglulu 37*91f16700Schasinglulu#endif /* ROCKCHIP_PLAT_LD_S */ 38