1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#ifndef ROCKCHIP_PLAT_LD_S 7*91f16700Schasinglulu#define ROCKCHIP_PLAT_LD_S 8*91f16700Schasinglulu 9*91f16700Schasinglulu#include <lib/xlat_tables/xlat_tables_defs.h> 10*91f16700Schasinglulu 11*91f16700SchasingluluMEMORY { 12*91f16700Schasinglulu SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE 13*91f16700Schasinglulu PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 14*91f16700Schasinglulu} 15*91f16700Schasinglulu 16*91f16700SchasingluluSECTIONS 17*91f16700Schasinglulu{ 18*91f16700Schasinglulu . = SRAM_BASE; 19*91f16700Schasinglulu ASSERT(. == ALIGN(PAGE_SIZE), 20*91f16700Schasinglulu "SRAM_BASE address is not aligned on a page boundary.") 21*91f16700Schasinglulu 22*91f16700Schasinglulu .text_sram : ALIGN(PAGE_SIZE) { 23*91f16700Schasinglulu __bl32_sram_text_start = .; 24*91f16700Schasinglulu *(.sram.text) 25*91f16700Schasinglulu *(.sram.rodata) 26*91f16700Schasinglulu __bl32_sram_text_real_end = .; 27*91f16700Schasinglulu . = ALIGN(PAGE_SIZE); 28*91f16700Schasinglulu __bl32_sram_text_end = .; 29*91f16700Schasinglulu } >SRAM 30*91f16700Schasinglulu ASSERT((__bl32_sram_text_real_end - __bl32_sram_text_start) <= 31*91f16700Schasinglulu SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit") 32*91f16700Schasinglulu 33*91f16700Schasinglulu .data_sram : ALIGN(PAGE_SIZE) { 34*91f16700Schasinglulu __bl32_sram_data_start = .; 35*91f16700Schasinglulu *(.sram.data) 36*91f16700Schasinglulu __bl32_sram_data_real_end = .; 37*91f16700Schasinglulu . = ALIGN(PAGE_SIZE); 38*91f16700Schasinglulu __bl32_sram_data_end = .; 39*91f16700Schasinglulu } >SRAM 40*91f16700Schasinglulu ASSERT((__bl32_sram_data_real_end - __bl32_sram_data_start) <= 41*91f16700Schasinglulu SRAM_DATA_LIMIT, ".data_sram has exceeded its limit") 42*91f16700Schasinglulu 43*91f16700Schasinglulu .stack_sram : ALIGN(PAGE_SIZE) { 44*91f16700Schasinglulu __bl32_sram_stack_start = .; 45*91f16700Schasinglulu . += PAGE_SIZE; 46*91f16700Schasinglulu __bl32_sram_stack_end = .; 47*91f16700Schasinglulu } >SRAM 48*91f16700Schasinglulu 49*91f16700Schasinglulu . = PMUSRAM_BASE; 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* 52*91f16700Schasinglulu * pmu_cpuson_entrypoint request address 53*91f16700Schasinglulu * align 64K when resume, so put it in the 54*91f16700Schasinglulu * start of pmusram 55*91f16700Schasinglulu */ 56*91f16700Schasinglulu .pmusram : { 57*91f16700Schasinglulu ASSERT(. == ALIGN(64 * 1024), 58*91f16700Schasinglulu ".pmusram.entry request 64K aligned."); 59*91f16700Schasinglulu *(.pmusram.entry) 60*91f16700Schasinglulu 61*91f16700Schasinglulu __bl32_pmusram_text_start = .; 62*91f16700Schasinglulu *(.pmusram.text) 63*91f16700Schasinglulu *(.pmusram.rodata) 64*91f16700Schasinglulu __bl32_pmusram_text_end = .; 65*91f16700Schasinglulu 66*91f16700Schasinglulu __bl32_pmusram_data_start = .; 67*91f16700Schasinglulu *(.pmusram.data) 68*91f16700Schasinglulu __bl32_pmusram_data_end = .; 69*91f16700Schasinglulu } >PMUSRAM 70*91f16700Schasinglulu} 71*91f16700Schasinglulu 72*91f16700Schasinglulu#endif /* ROCKCHIP_PLAT_LD_S */ 73