1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#ifndef __ROCKCHIP_PLAT_LD_S__ 8*91f16700Schasinglulu#define __ROCKCHIP_PLAT_LD_S__ 9*91f16700Schasinglulu 10*91f16700SchasingluluMEMORY { 11*91f16700Schasinglulu PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE 12*91f16700Schasinglulu} 13*91f16700Schasinglulu 14*91f16700SchasingluluSECTIONS 15*91f16700Schasinglulu{ 16*91f16700Schasinglulu . = PMUSRAM_BASE; 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* 19*91f16700Schasinglulu * pmu_cpuson_entrypoint request address 20*91f16700Schasinglulu * align 64K when resume, so put it in the 21*91f16700Schasinglulu * start of pmusram 22*91f16700Schasinglulu */ 23*91f16700Schasinglulu .pmusram : { 24*91f16700Schasinglulu ASSERT(. == ALIGN(64 * 1024), 25*91f16700Schasinglulu ".pmusram.entry request 64K aligned."); 26*91f16700Schasinglulu KEEP(*(.pmusram.entry)) 27*91f16700Schasinglulu 28*91f16700Schasinglulu __bl31_pmusram_text_start = .; 29*91f16700Schasinglulu *(.pmusram.text) 30*91f16700Schasinglulu *(.pmusram.rodata) 31*91f16700Schasinglulu __bl31_pmusram_text_end = .; 32*91f16700Schasinglulu __bl31_pmusram_data_start = .; 33*91f16700Schasinglulu *(.pmusram.data) 34*91f16700Schasinglulu __bl31_pmusram_data_end = .; 35*91f16700Schasinglulu } >PMUSRAM 36*91f16700Schasinglulu} 37*91f16700Schasinglulu 38*91f16700Schasinglulu#endif /* __ROCKCHIP_PLAT_LD_S__ */ 39