1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef __SOC_H__ 8*91f16700Schasinglulu #define __SOC_H__ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <plat_private.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #ifndef BITS_WMSK 13*91f16700Schasinglulu #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) 14*91f16700Schasinglulu #endif 15*91f16700Schasinglulu 16*91f16700Schasinglulu enum plls_id { 17*91f16700Schasinglulu APLL_ID = 0, 18*91f16700Schasinglulu DPLL_ID, 19*91f16700Schasinglulu CPLL_ID, 20*91f16700Schasinglulu NPLL_ID, 21*91f16700Schasinglulu GPLL_ID, 22*91f16700Schasinglulu END_PLL_ID, 23*91f16700Schasinglulu }; 24*91f16700Schasinglulu 25*91f16700Schasinglulu enum pll_mode { 26*91f16700Schasinglulu SLOW_MODE, 27*91f16700Schasinglulu NORM_MODE, 28*91f16700Schasinglulu DEEP_SLOW_MODE, 29*91f16700Schasinglulu }; 30*91f16700Schasinglulu 31*91f16700Schasinglulu /*************************************************************************** 32*91f16700Schasinglulu * GRF 33*91f16700Schasinglulu ***************************************************************************/ 34*91f16700Schasinglulu #define GRF_SOC_CON(i) (0x0400 + (i) * 4) 35*91f16700Schasinglulu #define GRF_PD_VO_CON0 0x0434 36*91f16700Schasinglulu #define GRF_SOC_STATUS0 0x0480 37*91f16700Schasinglulu #define GRF_CPU_STATUS0 0x0520 38*91f16700Schasinglulu #define GRF_CPU_STATUS1 0x0524 39*91f16700Schasinglulu #define GRF_SOC_NOC_CON0 0x0530 40*91f16700Schasinglulu #define GRF_SOC_NOC_CON1 0x0534 41*91f16700Schasinglulu 42*91f16700Schasinglulu #define CKECK_WFE_MSK 0x1 43*91f16700Schasinglulu #define CKECK_WFI_MSK 0x10 44*91f16700Schasinglulu #define CKECK_WFEI_MSK 0x11 45*91f16700Schasinglulu 46*91f16700Schasinglulu #define GRF_SOC_CON2_NSWDT_RST_EN 12 47*91f16700Schasinglulu 48*91f16700Schasinglulu /*************************************************************************** 49*91f16700Schasinglulu * cru 50*91f16700Schasinglulu ***************************************************************************/ 51*91f16700Schasinglulu #define CRU_MODE 0xa0 52*91f16700Schasinglulu #define CRU_MISC 0xa4 53*91f16700Schasinglulu #define CRU_GLB_CNT_TH 0xb0 54*91f16700Schasinglulu #define CRU_GLB_RST_ST 0xb4 55*91f16700Schasinglulu #define CRU_GLB_SRST_FST 0xb8 56*91f16700Schasinglulu #define CRU_GLB_SRST_SND 0xbc 57*91f16700Schasinglulu #define CRU_GLB_RST_CON 0xc0 58*91f16700Schasinglulu 59*91f16700Schasinglulu #define CRU_CLKSEL_CON 0x100 60*91f16700Schasinglulu #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + (i) * 4) 61*91f16700Schasinglulu #define CRU_CLKSEL_CON_CNT 60 62*91f16700Schasinglulu 63*91f16700Schasinglulu #define CRU_CLKGATE_CON 0x200 64*91f16700Schasinglulu #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4) 65*91f16700Schasinglulu #define CRU_CLKGATES_CON_CNT 18 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define CRU_SOFTRST_CON 0x300 68*91f16700Schasinglulu #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) 69*91f16700Schasinglulu #define CRU_SOFTRSTS_CON_CNT 12 70*91f16700Schasinglulu 71*91f16700Schasinglulu #define CRU_AUTOCS_CON0(id) (0x400 + (id) * 8) 72*91f16700Schasinglulu #define CRU_AUTOCS_CON1(id) (0x404 + (id) * 8) 73*91f16700Schasinglulu 74*91f16700Schasinglulu #define CRU_CONS_GATEID(i) (16 * (i)) 75*91f16700Schasinglulu #define GATE_ID(reg, bit) ((reg) * 16 + (bit)) 76*91f16700Schasinglulu 77*91f16700Schasinglulu #define CRU_GLB_SRST_FST_VALUE 0xfdb9 78*91f16700Schasinglulu #define CRU_GLB_SRST_SND_VALUE 0xeca8 79*91f16700Schasinglulu 80*91f16700Schasinglulu #define CRU_GLB_RST_TSADC_EXT 6 81*91f16700Schasinglulu #define CRU_GLB_RST_WDT_EXT 7 82*91f16700Schasinglulu 83*91f16700Schasinglulu #define CRU_GLB_CNT_RST_MSK 0xffff 84*91f16700Schasinglulu #define CRU_GLB_CNT_RST_1MS 0x5DC0 85*91f16700Schasinglulu 86*91f16700Schasinglulu #define CRU_GLB_RST_TSADC_FST BIT(0) 87*91f16700Schasinglulu #define CRU_GLB_RST_WDT_FST BIT(1) 88*91f16700Schasinglulu 89*91f16700Schasinglulu /*************************************************************************** 90*91f16700Schasinglulu * pll 91*91f16700Schasinglulu ***************************************************************************/ 92*91f16700Schasinglulu #define CRU_PLL_CONS(id, i) ((id) * 0x20 + (i) * 4) 93*91f16700Schasinglulu #define PLL_CON(i) ((i) * 4) 94*91f16700Schasinglulu #define PLL_CON_CNT 5 95*91f16700Schasinglulu #define PLL_LOCK_MSK BIT(10) 96*91f16700Schasinglulu #define PLL_MODE_SHIFT(id) ((id) == CPLL_ID ? \ 97*91f16700Schasinglulu 2 : \ 98*91f16700Schasinglulu ((id) == DPLL_ID ? 4 : 2 * (id))) 99*91f16700Schasinglulu #define PLL_MODE_MSK(id) (0x3 << PLL_MODE_SHIFT(id)) 100*91f16700Schasinglulu 101*91f16700Schasinglulu #define PLL_LOCKED_TIMEOUT 600000U 102*91f16700Schasinglulu 103*91f16700Schasinglulu /*************************************************************************** 104*91f16700Schasinglulu * GPIO 105*91f16700Schasinglulu ***************************************************************************/ 106*91f16700Schasinglulu #define SWPORTA_DR 0x00 107*91f16700Schasinglulu #define SWPORTA_DDR 0x04 108*91f16700Schasinglulu #define GPIO_INTEN 0x30 109*91f16700Schasinglulu #define GPIO_INT_STATUS 0x40 110*91f16700Schasinglulu #define GPIO_NUMS 4 111*91f16700Schasinglulu 112*91f16700Schasinglulu void clk_gate_con_save(uint32_t *clkgt_save); 113*91f16700Schasinglulu void clk_gate_con_restore(uint32_t *clkgt_save); 114*91f16700Schasinglulu void clk_gate_con_disable(void); 115*91f16700Schasinglulu 116*91f16700Schasinglulu void px30_soc_reset_config(void); 117*91f16700Schasinglulu 118*91f16700Schasinglulu #endif /* __SOC_H__ */ 119