1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SECURE_H 8*91f16700Schasinglulu #define SECURE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /*************************************************************************** 11*91f16700Schasinglulu * SGRF 12*91f16700Schasinglulu ***************************************************************************/ 13*91f16700Schasinglulu #define SGRF_SOC_CON(i) ((i) * 0x4) 14*91f16700Schasinglulu #define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4) 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define SGRF_MST_S_ALL_NS 0xffffffff 17*91f16700Schasinglulu #define SGRF_SLV_S_ALL_NS 0xffff0000 18*91f16700Schasinglulu #define DMA_IRQ_BOOT_NS 0xffffffff 19*91f16700Schasinglulu #define DMA_PERI_CH_NS_15_0 0xffffffff 20*91f16700Schasinglulu #define DMA_PERI_CH_NS_19_16 0x000f000f 21*91f16700Schasinglulu #define DMA_MANAGER_BOOT_NS 0x00010001 22*91f16700Schasinglulu #define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12) 23*91f16700Schasinglulu #define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /*************************************************************************** 26*91f16700Schasinglulu * DDR FIREWALL 27*91f16700Schasinglulu ***************************************************************************/ 28*91f16700Schasinglulu #define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4) 29*91f16700Schasinglulu #define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4) 30*91f16700Schasinglulu #define FIREWALL_DDR_FW_DDR_CON_REG 0x40 31*91f16700Schasinglulu #define FIREWALL_DDR_FW_DDR_RGN_NUM 8 32*91f16700Schasinglulu #define FIREWALL_DDR_FW_DDR_MST_NUM 6 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define PLAT_MAX_DDR_CAPACITY_MB 4096 35*91f16700Schasinglulu #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /************************************************** 38*91f16700Schasinglulu * secure timer 39*91f16700Schasinglulu **************************************************/ 40*91f16700Schasinglulu 41*91f16700Schasinglulu /* chanal0~5 */ 42*91f16700Schasinglulu #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 43*91f16700Schasinglulu 44*91f16700Schasinglulu #define TIMER_LOAD_COUNT0 0x0 45*91f16700Schasinglulu #define TIMER_LOAD_COUNT1 0x4 46*91f16700Schasinglulu 47*91f16700Schasinglulu #define TIMER_CUR_VALUE0 0x8 48*91f16700Schasinglulu #define TIMER_CUR_VALUE1 0xc 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define TIMER_CONTROL_REG 0x10 51*91f16700Schasinglulu #define TIMER_INTSTATUS 0x18 52*91f16700Schasinglulu 53*91f16700Schasinglulu #define TIMER_DIS 0x0 54*91f16700Schasinglulu #define TIMER_EN 0x1 55*91f16700Schasinglulu 56*91f16700Schasinglulu #define TIMER_FMODE (0x0 << 1) 57*91f16700Schasinglulu #define TIMER_RMODE (0x1 << 1) 58*91f16700Schasinglulu 59*91f16700Schasinglulu #define TIMER_LOAD_COUNT0_MSK (0xffffffff) 60*91f16700Schasinglulu #define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000) 61*91f16700Schasinglulu 62*91f16700Schasinglulu void secure_timer_init(void); 63*91f16700Schasinglulu void sgrf_init(void); 64*91f16700Schasinglulu 65*91f16700Schasinglulu #endif /* SECURE_H */ 66