1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <ddr_parameter.h> 9*91f16700Schasinglulu #include <plat_private.h> 10*91f16700Schasinglulu #include <secure.h> 11*91f16700Schasinglulu #include <px30_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /** 14*91f16700Schasinglulu * There are 8 regions for DDR security control 15*91f16700Schasinglulu * @rgn - the DDR regions 0 ~ 7 which are can be configured. 16*91f16700Schasinglulu * @st - start address to set as secure 17*91f16700Schasinglulu * @sz - length of area to set as secure 18*91f16700Schasinglulu * The internal unit is megabytes, so memory areas need to be aligned 19*91f16700Schasinglulu * to megabyte borders. 20*91f16700Schasinglulu */ 21*91f16700Schasinglulu static void secure_ddr_region(uint32_t rgn, 22*91f16700Schasinglulu uintptr_t st, size_t sz) 23*91f16700Schasinglulu { 24*91f16700Schasinglulu uintptr_t ed = st + sz; 25*91f16700Schasinglulu uintptr_t st_mb, ed_mb; 26*91f16700Schasinglulu uint32_t val; 27*91f16700Schasinglulu 28*91f16700Schasinglulu assert(rgn <= 7); 29*91f16700Schasinglulu assert(st < ed); 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* check aligned 1MB */ 32*91f16700Schasinglulu assert(st % SIZE_M(1) == 0); 33*91f16700Schasinglulu assert(ed % SIZE_M(1) == 0); 34*91f16700Schasinglulu 35*91f16700Schasinglulu st_mb = st / SIZE_M(1); 36*91f16700Schasinglulu ed_mb = ed / SIZE_M(1); 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* map top and base */ 39*91f16700Schasinglulu mmio_write_32(FIREWALL_DDR_BASE + 40*91f16700Schasinglulu FIREWALL_DDR_FW_DDR_RGN(rgn), 41*91f16700Schasinglulu RG_MAP_SECURE(ed_mb, st_mb)); 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* enable secure */ 44*91f16700Schasinglulu val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); 45*91f16700Schasinglulu val |= BIT(rgn); 46*91f16700Schasinglulu mmio_write_32(FIREWALL_DDR_BASE + 47*91f16700Schasinglulu FIREWALL_DDR_FW_DDR_CON_REG, val); 48*91f16700Schasinglulu } 49*91f16700Schasinglulu 50*91f16700Schasinglulu void secure_timer_init(void) 51*91f16700Schasinglulu { 52*91f16700Schasinglulu mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 53*91f16700Schasinglulu TIMER_DIS); 54*91f16700Schasinglulu 55*91f16700Schasinglulu mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); 56*91f16700Schasinglulu mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* auto reload & enable the timer */ 59*91f16700Schasinglulu mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, 60*91f16700Schasinglulu TIMER_EN | TIMER_FMODE); 61*91f16700Schasinglulu } 62*91f16700Schasinglulu 63*91f16700Schasinglulu void sgrf_init(void) 64*91f16700Schasinglulu { 65*91f16700Schasinglulu #ifdef PLAT_RK_SECURE_DDR_MINILOADER 66*91f16700Schasinglulu uint32_t i; 67*91f16700Schasinglulu struct param_ddr_usage usg; 68*91f16700Schasinglulu 69*91f16700Schasinglulu /* general secure regions */ 70*91f16700Schasinglulu usg = ddr_region_usage_parse(DDR_PARAM_BASE, 71*91f16700Schasinglulu PLAT_MAX_DDR_CAPACITY_MB); 72*91f16700Schasinglulu 73*91f16700Schasinglulu /* region-0 for TF-A, region-1 for optional OP-TEE */ 74*91f16700Schasinglulu assert(usg.s_nr < 7); 75*91f16700Schasinglulu 76*91f16700Schasinglulu for (i = 0; i < usg.s_nr; i++) 77*91f16700Schasinglulu secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]); 78*91f16700Schasinglulu #endif 79*91f16700Schasinglulu 80*91f16700Schasinglulu /* secure the trustzone ram */ 81*91f16700Schasinglulu secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE); 82*91f16700Schasinglulu 83*91f16700Schasinglulu /* set all slave ip into no-secure, except stimer */ 84*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); 85*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); 86*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); 87*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); 88*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); 89*91f16700Schasinglulu 90*91f16700Schasinglulu /* set master crypto to no-secure, dcf to secure */ 91*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); 92*91f16700Schasinglulu 93*91f16700Schasinglulu /* set DMAC into no-secure */ 94*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS); 95*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0); 96*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16); 97*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS); 98*91f16700Schasinglulu 99*91f16700Schasinglulu /* soft reset dma before use */ 100*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); 101*91f16700Schasinglulu udelay(5); 102*91f16700Schasinglulu mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); 103*91f16700Schasinglulu } 104