1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef __CPU_ON_FIXED_ADDR_H__ 8*91f16700Schasinglulu #define __CPU_ON_FIXED_ADDR_H__ 9*91f16700Schasinglulu 10*91f16700Schasinglulu /***************************************************************************** 11*91f16700Schasinglulu * define data offset in struct psram_data 12*91f16700Schasinglulu *****************************************************************************/ 13*91f16700Schasinglulu #define PSRAM_DT_SP 0x0 14*91f16700Schasinglulu #define PSRAM_DT_DDR_FUNC 0x8 15*91f16700Schasinglulu #define PSRAM_DT_DDR_DATA 0x10 16*91f16700Schasinglulu #define PSRAM_DT_DDRFLAG 0x18 17*91f16700Schasinglulu #define PSRAM_DT_MPIDR 0x1c 18*91f16700Schasinglulu #define PSRAM_DT_PM_FLAG 0x20 19*91f16700Schasinglulu #define PSRAM_DT_END 0x24 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* reserve 4 byte */ 22*91f16700Schasinglulu #define PSRAM_DT_END_RES4 (PSRAM_DT_END + 4) 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define PSRAM_DT_SIZE_WORDS (PSRAM_DT_END_RES4 / 4) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define PM_WARM_BOOT_SHT 0 27*91f16700Schasinglulu #define PM_WARM_BOOT_BIT (1 << PM_WARM_BOOT_SHT) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #ifndef __ASSEMBLER__ 30*91f16700Schasinglulu 31*91f16700Schasinglulu struct psram_data_t { 32*91f16700Schasinglulu uint64_t sp; 33*91f16700Schasinglulu uint64_t ddr_func; 34*91f16700Schasinglulu uint64_t ddr_data; 35*91f16700Schasinglulu uint32_t ddr_flag; 36*91f16700Schasinglulu uint32_t boot_mpidr; 37*91f16700Schasinglulu uint32_t pm_flag; 38*91f16700Schasinglulu }; 39*91f16700Schasinglulu 40*91f16700Schasinglulu CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP, 41*91f16700Schasinglulu assert_psram_dt_sp_offset_mistmatch); 42*91f16700Schasinglulu CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC, 43*91f16700Schasinglulu assert_psram_dt_ddr_func_offset_mistmatch); 44*91f16700Schasinglulu CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA, 45*91f16700Schasinglulu assert_psram_dt_ddr_data_offset_mistmatch); 46*91f16700Schasinglulu CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG, 47*91f16700Schasinglulu assert_psram_dt_ddr_flag_offset_mistmatch); 48*91f16700Schasinglulu CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR, 49*91f16700Schasinglulu assert_psram_dt_mpidr_offset_mistmatch); 50*91f16700Schasinglulu 51*91f16700Schasinglulu extern struct psram_data_t sys_sleep_flag_sram; 52*91f16700Schasinglulu 53*91f16700Schasinglulu #endif /* __ASSEMBLER__ */ 54*91f16700Schasinglulu 55*91f16700Schasinglulu #endif 56