1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <platform_def.h> 10*91f16700Schasinglulu#include <cpus_on_fixed_addr.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .globl sys_sleep_flag_sram 13*91f16700Schasinglulu .globl pmu_cpuson_entrypoint 14*91f16700Schasinglulu 15*91f16700Schasinglulu .macro pmusram_entry_func _name 16*91f16700Schasinglulu .section .pmusram.entry, "ax" 17*91f16700Schasinglulu .type \_name, %function 18*91f16700Schasinglulu .cfi_startproc 19*91f16700Schasinglulu \_name: 20*91f16700Schasinglulu .endm 21*91f16700Schasinglulu 22*91f16700Schasinglulupmusram_entry_func pmu_cpuson_entrypoint 23*91f16700Schasinglulu adr x5, sys_sleep_flag_sram 24*91f16700Schasinglulu ldr w2, [x5, #PSRAM_DT_PM_FLAG] 25*91f16700Schasinglulu 26*91f16700Schasinglulu tbz w2, #PM_WARM_BOOT_SHT, sys_resume_sp 27*91f16700Schasinglulu ldr x1, =platform_cpu_warmboot 28*91f16700Schasinglulu br x1 29*91f16700Schasinglulusys_resume_sp: 30*91f16700Schasinglulu adr x5, sys_sleep_flag_sram 31*91f16700Schasinglulu ldr x1, [x5, #PSRAM_DT_SP] 32*91f16700Schasinglulu mov sp, x1 33*91f16700Schasingluluddr_resume: 34*91f16700Schasinglulu ldr x1, [x5, #PSRAM_DT_DDR_FUNC] 35*91f16700Schasinglulu cmp x1, #0 36*91f16700Schasinglulu b.eq sys_resume 37*91f16700Schasinglulu blr x1 38*91f16700Schasinglulusys_resume: 39*91f16700Schasinglulu ldr x1, =bl31_warm_entrypoint 40*91f16700Schasinglulu br x1 41*91f16700Schasingluluendfunc pmu_cpuson_entrypoint 42*91f16700Schasinglulu 43*91f16700Schasinglulu .section .pmusram.data, "a" 44*91f16700Schasinglulu .align 3 45*91f16700Schasinglulusys_sleep_flag_sram: 46*91f16700Schasinglulu .rept PSRAM_DT_SIZE_WORDS 47*91f16700Schasinglulu .word 0 48*91f16700Schasinglulu .endr 49