xref: /arm-trusted-firmware/plat/rockchip/common/bl31_plat_setup.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #include <assert.h>
8*91f16700Schasinglulu 
9*91f16700Schasinglulu #include <platform_def.h>
10*91f16700Schasinglulu 
11*91f16700Schasinglulu #include <common/bl_common.h>
12*91f16700Schasinglulu #include <common/debug.h>
13*91f16700Schasinglulu #include <common/desc_image_load.h>
14*91f16700Schasinglulu #include <drivers/console.h>
15*91f16700Schasinglulu #include <drivers/generic_delay_timer.h>
16*91f16700Schasinglulu #include <drivers/ti/uart/uart_16550.h>
17*91f16700Schasinglulu #include <lib/mmio.h>
18*91f16700Schasinglulu #include <plat_private.h>
19*91f16700Schasinglulu #include <plat/common/platform.h>
20*91f16700Schasinglulu 
21*91f16700Schasinglulu static entry_point_info_t bl32_ep_info;
22*91f16700Schasinglulu static entry_point_info_t bl33_ep_info;
23*91f16700Schasinglulu 
24*91f16700Schasinglulu /*******************************************************************************
25*91f16700Schasinglulu  * Return a pointer to the 'entry_point_info' structure of the next image for
26*91f16700Schasinglulu  * the security state specified. BL33 corresponds to the non-secure image type
27*91f16700Schasinglulu  * while BL32 corresponds to the secure image type. A NULL pointer is returned
28*91f16700Schasinglulu  * if the image does not exist.
29*91f16700Schasinglulu  ******************************************************************************/
30*91f16700Schasinglulu entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
31*91f16700Schasinglulu {
32*91f16700Schasinglulu 	entry_point_info_t *next_image_info;
33*91f16700Schasinglulu 
34*91f16700Schasinglulu 	next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
35*91f16700Schasinglulu 	assert(next_image_info->h.type == PARAM_EP);
36*91f16700Schasinglulu 
37*91f16700Schasinglulu 	/* None of the images on this platform can have 0x0 as the entrypoint */
38*91f16700Schasinglulu 	if (next_image_info->pc)
39*91f16700Schasinglulu 		return next_image_info;
40*91f16700Schasinglulu 	else
41*91f16700Schasinglulu 		return NULL;
42*91f16700Schasinglulu }
43*91f16700Schasinglulu 
44*91f16700Schasinglulu #pragma weak params_early_setup
45*91f16700Schasinglulu void params_early_setup(u_register_t plat_param_from_bl2)
46*91f16700Schasinglulu {
47*91f16700Schasinglulu }
48*91f16700Schasinglulu 
49*91f16700Schasinglulu /*******************************************************************************
50*91f16700Schasinglulu  * Perform any BL3-1 early platform setup. Here is an opportunity to copy
51*91f16700Schasinglulu  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
52*91f16700Schasinglulu  * are lost (potentially). This needs to be done before the MMU is initialized
53*91f16700Schasinglulu  * so that the memory layout can be used while creating page tables.
54*91f16700Schasinglulu  * BL2 has flushed this information to memory, so we are guaranteed to pick up
55*91f16700Schasinglulu  * good data.
56*91f16700Schasinglulu  ******************************************************************************/
57*91f16700Schasinglulu void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
58*91f16700Schasinglulu 				u_register_t arg2, u_register_t arg3)
59*91f16700Schasinglulu {
60*91f16700Schasinglulu 	static console_t console;
61*91f16700Schasinglulu 
62*91f16700Schasinglulu 	params_early_setup(arg1);
63*91f16700Schasinglulu 
64*91f16700Schasinglulu 	if (rockchip_get_uart_base() != 0)
65*91f16700Schasinglulu 		console_16550_register(rockchip_get_uart_base(),
66*91f16700Schasinglulu 				       rockchip_get_uart_clock(),
67*91f16700Schasinglulu 				       rockchip_get_uart_baudrate(), &console);
68*91f16700Schasinglulu 
69*91f16700Schasinglulu 	VERBOSE("bl31_setup\n");
70*91f16700Schasinglulu 
71*91f16700Schasinglulu 	bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
72*91f16700Schasinglulu }
73*91f16700Schasinglulu 
74*91f16700Schasinglulu /*******************************************************************************
75*91f16700Schasinglulu  * Perform any BL3-1 platform setup code
76*91f16700Schasinglulu  ******************************************************************************/
77*91f16700Schasinglulu void bl31_platform_setup(void)
78*91f16700Schasinglulu {
79*91f16700Schasinglulu 	generic_delay_timer_init();
80*91f16700Schasinglulu 	plat_rockchip_soc_init();
81*91f16700Schasinglulu 
82*91f16700Schasinglulu 	/* Initialize the gic cpu and distributor interfaces */
83*91f16700Schasinglulu 	plat_rockchip_gic_driver_init();
84*91f16700Schasinglulu 	plat_rockchip_gic_init();
85*91f16700Schasinglulu 	plat_rockchip_pmu_init();
86*91f16700Schasinglulu }
87*91f16700Schasinglulu 
88*91f16700Schasinglulu /*******************************************************************************
89*91f16700Schasinglulu  * Perform the very early platform specific architectural setup here. At the
90*91f16700Schasinglulu  * moment this is only initializes the mmu in a quick and dirty way.
91*91f16700Schasinglulu  ******************************************************************************/
92*91f16700Schasinglulu void bl31_plat_arch_setup(void)
93*91f16700Schasinglulu {
94*91f16700Schasinglulu 	plat_cci_init();
95*91f16700Schasinglulu 	plat_cci_enable();
96*91f16700Schasinglulu 	plat_configure_mmu_el3(BL_CODE_BASE,
97*91f16700Schasinglulu 			       BL_COHERENT_RAM_END - BL_CODE_BASE,
98*91f16700Schasinglulu 			       BL_CODE_BASE,
99*91f16700Schasinglulu 			       BL_CODE_END,
100*91f16700Schasinglulu 			       BL_COHERENT_RAM_BASE,
101*91f16700Schasinglulu 			       BL_COHERENT_RAM_END);
102*91f16700Schasinglulu }
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