1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <string.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <arch_helpers.h> 12*91f16700Schasinglulu #include <common/bl_common.h> 13*91f16700Schasinglulu #include <common/debug.h> 14*91f16700Schasinglulu #include <drivers/arm/cci.h> 15*91f16700Schasinglulu #include <lib/utils.h> 16*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu #include <plat_private.h> 19*91f16700Schasinglulu 20*91f16700Schasinglulu #ifdef PLAT_RK_CCI_BASE 21*91f16700Schasinglulu static const int cci_map[] = { 22*91f16700Schasinglulu PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX, 23*91f16700Schasinglulu PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu #endif 26*91f16700Schasinglulu 27*91f16700Schasinglulu /****************************************************************************** 28*91f16700Schasinglulu * Macro generating the code for the function setting up the pagetables as per 29*91f16700Schasinglulu * the platform memory map & initialize the mmu, for the given exception level 30*91f16700Schasinglulu ******************************************************************************/ 31*91f16700Schasinglulu #define DEFINE_CONFIGURE_MMU_EL(_el) \ 32*91f16700Schasinglulu void plat_configure_mmu_el ## _el(unsigned long total_base, \ 33*91f16700Schasinglulu unsigned long total_size, \ 34*91f16700Schasinglulu unsigned long ro_start, \ 35*91f16700Schasinglulu unsigned long ro_limit, \ 36*91f16700Schasinglulu unsigned long coh_start, \ 37*91f16700Schasinglulu unsigned long coh_limit) \ 38*91f16700Schasinglulu { \ 39*91f16700Schasinglulu mmap_add_region(total_base, total_base, \ 40*91f16700Schasinglulu total_size, \ 41*91f16700Schasinglulu MT_MEMORY | MT_RW | MT_SECURE); \ 42*91f16700Schasinglulu mmap_add_region(ro_start, ro_start, \ 43*91f16700Schasinglulu ro_limit - ro_start, \ 44*91f16700Schasinglulu MT_MEMORY | MT_RO | MT_SECURE); \ 45*91f16700Schasinglulu mmap_add_region(coh_start, coh_start, \ 46*91f16700Schasinglulu coh_limit - coh_start, \ 47*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE); \ 48*91f16700Schasinglulu mmap_add(plat_rk_mmap); \ 49*91f16700Schasinglulu rockchip_plat_mmu_el##_el(); \ 50*91f16700Schasinglulu init_xlat_tables(); \ 51*91f16700Schasinglulu \ 52*91f16700Schasinglulu enable_mmu_el ## _el(0); \ 53*91f16700Schasinglulu } 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* Define EL3 variants of the function initialising the MMU */ 56*91f16700Schasinglulu DEFINE_CONFIGURE_MMU_EL(3) 57*91f16700Schasinglulu 58*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 59*91f16700Schasinglulu { 60*91f16700Schasinglulu return SYS_COUNTER_FREQ_IN_TICKS; 61*91f16700Schasinglulu } 62*91f16700Schasinglulu 63*91f16700Schasinglulu void plat_cci_init(void) 64*91f16700Schasinglulu { 65*91f16700Schasinglulu #ifdef PLAT_RK_CCI_BASE 66*91f16700Schasinglulu /* Initialize CCI driver */ 67*91f16700Schasinglulu cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 68*91f16700Schasinglulu #endif 69*91f16700Schasinglulu } 70*91f16700Schasinglulu 71*91f16700Schasinglulu void plat_cci_enable(void) 72*91f16700Schasinglulu { 73*91f16700Schasinglulu /* 74*91f16700Schasinglulu * Enable CCI coherency for this cluster. 75*91f16700Schasinglulu * No need for locks as no other cpu is active at the moment. 76*91f16700Schasinglulu */ 77*91f16700Schasinglulu #ifdef PLAT_RK_CCI_BASE 78*91f16700Schasinglulu cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 79*91f16700Schasinglulu #endif 80*91f16700Schasinglulu } 81*91f16700Schasinglulu 82*91f16700Schasinglulu void plat_cci_disable(void) 83*91f16700Schasinglulu { 84*91f16700Schasinglulu #ifdef PLAT_RK_CCI_BASE 85*91f16700Schasinglulu cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 86*91f16700Schasinglulu #endif 87*91f16700Schasinglulu } 88