1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <string.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <arch_helpers.h> 12*91f16700Schasinglulu #include <common/bl_common.h> 13*91f16700Schasinglulu #include <common/debug.h> 14*91f16700Schasinglulu #include <lib/utils.h> 15*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables.h> 16*91f16700Schasinglulu 17*91f16700Schasinglulu #include <plat_private.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu void plat_configure_mmu_svc_mon(unsigned long total_base, 20*91f16700Schasinglulu unsigned long total_size, 21*91f16700Schasinglulu unsigned long ro_start, 22*91f16700Schasinglulu unsigned long ro_limit, 23*91f16700Schasinglulu unsigned long coh_start, 24*91f16700Schasinglulu unsigned long coh_limit) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu mmap_add_region(total_base, total_base, total_size, 27*91f16700Schasinglulu MT_MEMORY | MT_RW | MT_SECURE); 28*91f16700Schasinglulu mmap_add_region(ro_start, ro_start, ro_limit - ro_start, 29*91f16700Schasinglulu MT_MEMORY | MT_RO | MT_SECURE); 30*91f16700Schasinglulu mmap_add_region(coh_start, coh_start, coh_limit - coh_start, 31*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE); 32*91f16700Schasinglulu mmap_add(plat_rk_mmap); 33*91f16700Schasinglulu rockchip_plat_mmu_svc_mon(); 34*91f16700Schasinglulu init_xlat_tables(); 35*91f16700Schasinglulu enable_mmu_svc_mon(0); 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 39*91f16700Schasinglulu { 40*91f16700Schasinglulu return SYS_COUNTER_FREQ_IN_TICKS; 41*91f16700Schasinglulu } 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* 44*91f16700Schasinglulu * generic pm code does cci handling, but rockchip arm32 platforms 45*91f16700Schasinglulu * have ever only 1 cluster, so nothing to do. 46*91f16700Schasinglulu */ 47*91f16700Schasinglulu void plat_cci_init(void) 48*91f16700Schasinglulu { 49*91f16700Schasinglulu } 50*91f16700Schasinglulu 51*91f16700Schasinglulu void plat_cci_enable(void) 52*91f16700Schasinglulu { 53*91f16700Schasinglulu } 54*91f16700Schasinglulu 55*91f16700Schasinglulu void plat_cci_disable(void) 56*91f16700Schasinglulu { 57*91f16700Schasinglulu } 58