1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef RCAR_PRIVATE_H 8*91f16700Schasinglulu #define RCAR_PRIVATE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <common/bl_common.h> 11*91f16700Schasinglulu #include <lib/bakery_lock.h> 12*91f16700Schasinglulu #include <lib/el3_runtime/cpu_data.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <platform_def.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu typedef volatile struct mailbox { 17*91f16700Schasinglulu unsigned long value __aligned(CACHE_WRITEBACK_GRANULE); 18*91f16700Schasinglulu } mailbox_t; 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* 21*91f16700Schasinglulu * This structure represents the superset of information that is passed to 22*91f16700Schasinglulu * BL31 e.g. while passing control to it from BL2 which is bl31_params 23*91f16700Schasinglulu * and bl31_plat_params and its elements 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu typedef struct bl2_to_bl31_params_mem { 26*91f16700Schasinglulu image_info_t bl32_image_info; 27*91f16700Schasinglulu image_info_t bl33_image_info; 28*91f16700Schasinglulu entry_point_info_t bl33_ep_info; 29*91f16700Schasinglulu entry_point_info_t bl32_ep_info; 30*91f16700Schasinglulu } bl2_to_bl31_params_mem_t; 31*91f16700Schasinglulu 32*91f16700Schasinglulu #if USE_COHERENT_MEM 33*91f16700Schasinglulu #define RCAR_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(rcar_lock); 34*91f16700Schasinglulu #define rcar_lock_init() bakery_lock_init(&rcar_lock) 35*91f16700Schasinglulu #define rcar_lock_get() bakery_lock_get(&rcar_lock) 36*91f16700Schasinglulu #define rcar_lock_release() bakery_lock_release(&rcar_lock) 37*91f16700Schasinglulu #else 38*91f16700Schasinglulu /* 39*91f16700Schasinglulu * Constants to specify how many bakery locks this platform implements. These 40*91f16700Schasinglulu * are used if the platform chooses not to use coherent memory for bakery lock 41*91f16700Schasinglulu * data structures. 42*91f16700Schasinglulu */ 43*91f16700Schasinglulu #define RCAR_MAX_BAKERIES 2 44*91f16700Schasinglulu #define RCAR_PWRC_BAKERY_ID 0 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* 47*91f16700Schasinglulu * Definition of structure which holds platform specific per-cpu data. Currently 48*91f16700Schasinglulu * it holds only the bakery lock information for each cpu. Constants to 49*91f16700Schasinglulu * specify how many bakeries this platform implements and bakery ids are 50*91f16700Schasinglulu * specified in rcar_def.h 51*91f16700Schasinglulu */ 52*91f16700Schasinglulu typedef struct rcar_cpu_data { 53*91f16700Schasinglulu bakery_info_t pcpu_bakery_info[RCAR_MAX_BAKERIES]; 54*91f16700Schasinglulu } rcar_cpu_data_t; 55*91f16700Schasinglulu 56*91f16700Schasinglulu #define RCAR_CPU_DATA_LOCK_OFFSET \ 57*91f16700Schasinglulu __builtin_offsetof(rcar_cpu_data_t, pcpu_bakery_info) 58*91f16700Schasinglulu /* 59*91f16700Schasinglulu * Helper macros for bakery lock api when using the above rcar_cpu_data_t for 60*91f16700Schasinglulu * bakery lock data structures. It assumes that the bakery_info is at the 61*91f16700Schasinglulu * beginning of the platform specific per-cpu data. 62*91f16700Schasinglulu */ 63*91f16700Schasinglulu #define rcar_lock_init(_lock_arg) 64*91f16700Schasinglulu 65*91f16700Schasinglulu #define rcar_lock_get(_lock_arg) \ 66*91f16700Schasinglulu bakery_lock_get(_lock_arg, \ 67*91f16700Schasinglulu CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET) 68*91f16700Schasinglulu 69*91f16700Schasinglulu #define rcar_lock_release(_lock_arg) \ 70*91f16700Schasinglulu bakery_lock_release(_lock_arg, \ 71*91f16700Schasinglulu CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET) 72*91f16700Schasinglulu /* 73*91f16700Schasinglulu * Ensure that the size of the RCAR specific per-cpu data structure and the size 74*91f16700Schasinglulu * of the memory allocated in generic per-cpu data for the platform are the same 75*91f16700Schasinglulu */ 76*91f16700Schasinglulu CASSERT(sizeof(rcar_cpu_data_t) == PLAT_PCPU_DATA_SIZE, 77*91f16700Schasinglulu rcar_pcpu_data_size_mismatch); 78*91f16700Schasinglulu #endif 79*91f16700Schasinglulu /* 80*91f16700Schasinglulu * Function and variable prototypes 81*91f16700Schasinglulu */ 82*91f16700Schasinglulu void rcar_configure_mmu_el3(unsigned long total_base, 83*91f16700Schasinglulu unsigned long total_size, 84*91f16700Schasinglulu unsigned long ro_start, unsigned long ro_limit 85*91f16700Schasinglulu #if USE_COHERENT_MEM 86*91f16700Schasinglulu , unsigned long coh_start, unsigned long coh_limit 87*91f16700Schasinglulu #endif 88*91f16700Schasinglulu ); 89*91f16700Schasinglulu 90*91f16700Schasinglulu void rcar_setup_topology(void); 91*91f16700Schasinglulu void rcar_cci_disable(void); 92*91f16700Schasinglulu void rcar_cci_enable(void); 93*91f16700Schasinglulu void rcar_cci_init(void); 94*91f16700Schasinglulu 95*91f16700Schasinglulu void plat_invalidate_icache(void); 96*91f16700Schasinglulu void plat_cci_disable(void); 97*91f16700Schasinglulu void plat_cci_enable(void); 98*91f16700Schasinglulu void plat_cci_init(void); 99*91f16700Schasinglulu 100*91f16700Schasinglulu void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit); 101*91f16700Schasinglulu void cpg_write(uintptr_t regadr, uint32_t regval); 102*91f16700Schasinglulu 103*91f16700Schasinglulu void rcar_console_boot_init(void); 104*91f16700Schasinglulu void rcar_console_boot_end(void); 105*91f16700Schasinglulu void rcar_console_runtime_init(void); 106*91f16700Schasinglulu void rcar_console_runtime_end(void); 107*91f16700Schasinglulu 108*91f16700Schasinglulu #endif /* RCAR_PRIVATE_H */ 109