1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu 7*91f16700Schasingluluinclude drivers/arm/gic/v2/gicv2.mk 8*91f16700Schasingluluinclude lib/xlat_tables_v2/xlat_tables.mk 9*91f16700Schasinglulu 10*91f16700SchasingluluPLAT_BL_COMMON_SOURCES := ${GICV2_SOURCES} \ 11*91f16700Schasinglulu ${XLAT_TABLES_LIB_SRCS} \ 12*91f16700Schasinglulu drivers/delay_timer/delay_timer.c \ 13*91f16700Schasinglulu drivers/delay_timer/generic_delay_timer.c \ 14*91f16700Schasinglulu plat/common/plat_gicv2.c \ 15*91f16700Schasinglulu plat/qti/msm8916/msm8916_gicv2.c \ 16*91f16700Schasinglulu plat/qti/msm8916/msm8916_setup.c \ 17*91f16700Schasinglulu plat/qti/msm8916/${ARCH}/msm8916_helpers.S \ 18*91f16700Schasinglulu plat/qti/msm8916/${ARCH}/uartdm_console.S 19*91f16700Schasinglulu 20*91f16700SchasingluluMSM8916_CPU := $(if ${ARM_CORTEX_A7},cortex_a7,cortex_a53) 21*91f16700SchasingluluMSM8916_PM_SOURCES := drivers/arm/cci/cci.c \ 22*91f16700Schasinglulu lib/cpus/${ARCH}/${MSM8916_CPU}.S \ 23*91f16700Schasinglulu plat/common/plat_psci_common.c \ 24*91f16700Schasinglulu plat/qti/msm8916/msm8916_config.c \ 25*91f16700Schasinglulu plat/qti/msm8916/msm8916_cpu_boot.c \ 26*91f16700Schasinglulu plat/qti/msm8916/msm8916_pm.c \ 27*91f16700Schasinglulu plat/qti/msm8916/msm8916_topology.c 28*91f16700Schasinglulu 29*91f16700SchasingluluBL31_SOURCES += ${MSM8916_PM_SOURCES} \ 30*91f16700Schasinglulu plat/qti/msm8916/msm8916_bl31_setup.c 31*91f16700Schasinglulu 32*91f16700SchasingluluPLAT_INCLUDES := -Iplat/qti/msm8916/include 33*91f16700Schasinglulu 34*91f16700Schasingluluifeq (${ARCH},aarch64) 35*91f16700Schasinglulu# arm_macros.S exists only on aarch64 currently 36*91f16700SchasingluluPLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} 37*91f16700Schasingluluendif 38*91f16700Schasinglulu 39*91f16700Schasinglulu# Only BL31 is supported at the moment and is entered on a single CPU 40*91f16700SchasingluluRESET_TO_BL31 := 1 41*91f16700SchasingluluCOLD_BOOT_SINGLE_CPU := 1 42*91f16700Schasinglulu 43*91f16700Schasinglulu# Have different sections for code and rodata 44*91f16700SchasingluluSEPARATE_CODE_AND_RODATA := 1 45*91f16700Schasinglulu 46*91f16700Schasinglulu# Single cluster 47*91f16700SchasingluluWARMBOOT_ENABLE_DCACHE_EARLY := 1 48*91f16700Schasinglulu 49*91f16700Schasinglulu# Disable features unsupported in ARMv8.0 50*91f16700SchasingluluENABLE_SPE_FOR_NS := 0 51*91f16700SchasingluluENABLE_SVE_FOR_NS := 0 52*91f16700Schasinglulu 53*91f16700Schasinglulu# Disable workarounds unnecessary for Cortex-A7/A53 54*91f16700SchasingluluWORKAROUND_CVE_2017_5715 := 0 55*91f16700SchasingluluWORKAROUND_CVE_2022_23960 := 0 56*91f16700Schasinglulu 57*91f16700Schasingluluifeq (${MSM8916_CPU},cortex_a53) 58*91f16700Schasinglulu# The Cortex-A53 revision varies depending on the SoC revision. 59*91f16700Schasinglulu# msm8916 uses r0p0, msm8939 uses r0p1 or r0p4. Enable all errata 60*91f16700Schasinglulu# and rely on the runtime detection to apply them only if needed. 61*91f16700SchasingluluERRATA_A53_819472 := 1 62*91f16700SchasingluluERRATA_A53_824069 := 1 63*91f16700SchasingluluERRATA_A53_826319 := 1 64*91f16700SchasingluluERRATA_A53_827319 := 1 65*91f16700SchasingluluERRATA_A53_835769 := 1 66*91f16700SchasingluluERRATA_A53_836870 := 1 67*91f16700SchasingluluERRATA_A53_843419 := 1 68*91f16700SchasingluluERRATA_A53_855873 := 1 69*91f16700SchasingluluERRATA_A53_1530924 := 1 70*91f16700Schasingluluendif 71*91f16700Schasinglulu 72*91f16700Schasinglulu# Build config flags 73*91f16700Schasinglulu# ------------------ 74*91f16700SchasingluluBL31_BASE ?= 0x86500000 75*91f16700SchasingluluPRELOADED_BL33_BASE ?= 0x8f600000 76*91f16700Schasinglulu 77*91f16700Schasingluluifeq (${ARCH},aarch64) 78*91f16700Schasinglulu BL32_BASE ?= BL31_LIMIT 79*91f16700Schasinglulu $(eval $(call add_define,BL31_BASE)) 80*91f16700Schasingluluelse 81*91f16700Schasinglulu ifeq (${AARCH32_SP},none) 82*91f16700Schasinglulu $(error Variable AARCH32_SP has to be set for AArch32) 83*91f16700Schasinglulu endif 84*91f16700Schasinglulu # There is no BL31 on aarch32, so reuse its location for BL32 85*91f16700Schasinglulu BL32_BASE ?= $(BL31_BASE) 86*91f16700Schasingluluendif 87*91f16700Schasinglulu$(eval $(call add_define,BL32_BASE)) 88*91f16700Schasinglulu 89*91f16700Schasinglulu# UART number to use for TF-A output during early boot 90*91f16700SchasingluluQTI_UART_NUM ?= 2 91*91f16700Schasinglulu$(eval $(call assert_numeric,QTI_UART_NUM)) 92*91f16700Schasinglulu$(eval $(call add_define,QTI_UART_NUM)) 93*91f16700Schasinglulu 94*91f16700Schasinglulu# Set to 1 on the command line to keep using UART after early boot. 95*91f16700Schasinglulu# Requires reserving the UART and related clocks inside the normal world. 96*91f16700SchasingluluQTI_RUNTIME_UART ?= 0 97*91f16700Schasinglulu$(eval $(call assert_boolean,QTI_RUNTIME_UART)) 98*91f16700Schasinglulu$(eval $(call add_define,QTI_RUNTIME_UART)) 99