1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 7*91f16700Schasinglulu #define PLATFORM_DEF_H 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <plat/common/common_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #ifdef __aarch64__ 12*91f16700Schasinglulu /* 13*91f16700Schasinglulu * There is at least 1 MiB available for BL31. However, at the moment the 14*91f16700Schasinglulu * "msm8916_entry_point" variable in the data section is read through the 15*91f16700Schasinglulu * 64 KiB region of the "boot remapper" after reset. For simplicity, limit 16*91f16700Schasinglulu * the end of the data section (BL31_PROGBITS_LIMIT) to 64 KiB for now and 17*91f16700Schasinglulu * the overall limit to 128 KiB. This could be increased if needed by placing 18*91f16700Schasinglulu * the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31. 19*91f16700Schasinglulu */ 20*91f16700Schasinglulu #define BL31_LIMIT (BL31_BASE + SZ_128K) 21*91f16700Schasinglulu #define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K) 22*91f16700Schasinglulu #endif 23*91f16700Schasinglulu #define BL32_LIMIT (BL32_BASE + SZ_128K) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE U(64) 26*91f16700Schasinglulu #define PLATFORM_STACK_SIZE SZ_4K 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* CPU topology: one or two clusters with 4 cores each */ 29*91f16700Schasinglulu #ifdef PLAT_msm8939 30*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(2) 31*91f16700Schasinglulu #else 32*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(1) 33*91f16700Schasinglulu #endif 34*91f16700Schasinglulu #if defined(PLAT_mdm9607) 35*91f16700Schasinglulu #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(0) /* 1 */ 36*91f16700Schasinglulu #else 37*91f16700Schasinglulu #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2) /* 4 */ 38*91f16700Schasinglulu #endif 39*91f16700Schasinglulu #define PLATFORM_CPUS_PER_CLUSTER (1 << PLATFORM_CPU_PER_CLUSTER_SHIFT) 40*91f16700Schasinglulu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 41*91f16700Schasinglulu PLATFORM_CPUS_PER_CLUSTER) 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* Power management */ 44*91f16700Schasinglulu #define PLATFORM_SYSTEM_COUNT U(1) 45*91f16700Schasinglulu #define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \ 46*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT + \ 47*91f16700Schasinglulu PLATFORM_CORE_COUNT) 48*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 49*91f16700Schasinglulu #define PLAT_MAX_RET_STATE U(2) 50*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE U(3) 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* Translation tables */ 53*91f16700Schasinglulu #define MAX_MMAP_REGIONS 8 54*91f16700Schasinglulu #define MAX_XLAT_TABLES 4 55*91f16700Schasinglulu 56*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 57*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* Timer */ 60*91f16700Schasinglulu #define PLAT_SYSCNT_FREQ 19200000 61*91f16700Schasinglulu #define IRQ_SEC_PHY_TIMER (16 + 2) /* PPI #2 */ 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* 64*91f16700Schasinglulu * The Qualcomm QGIC2 implementation seems to have PIDR0-4 and PIDR4-7 65*91f16700Schasinglulu * erroneously swapped for some reason. PIDR2 is actually at 0xFD8. 66*91f16700Schasinglulu * Override the address in <drivers/arm/gicv2.h> to avoid a failing assert(). 67*91f16700Schasinglulu */ 68*91f16700Schasinglulu #define GICD_PIDR2_GICV2 U(0xFD8) 69*91f16700Schasinglulu 70*91f16700Schasinglulu /* TSP */ 71*91f16700Schasinglulu #define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER 72*91f16700Schasinglulu #define TSP_SEC_MEM_BASE BL32_BASE 73*91f16700Schasinglulu #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 74*91f16700Schasinglulu 75*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 76