1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MSM8916_MMAP_H 8*91f16700Schasinglulu #define MSM8916_MMAP_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define PCNOC_BASE 0x00000000 11*91f16700Schasinglulu #define PCNOC_SIZE SZ_128M 12*91f16700Schasinglulu #define APCS_BASE 0x0b000000 13*91f16700Schasinglulu #define APCS_SIZE SZ_8M 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define MPM_BASE (PCNOC_BASE + 0x04a0000) 16*91f16700Schasinglulu #define MPM_PS_HOLD (MPM_BASE + 0xb000) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define TLMM_BASE (PCNOC_BASE + 0x1000000) 19*91f16700Schasinglulu #define TLMM_GPIO_CFG(n) (TLMM_BASE + ((n) * 0x1000)) 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define GCC_BASE (PCNOC_BASE + 0x1800000) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define APPS_SMMU_BASE (PCNOC_BASE + 0x1e00000) 24*91f16700Schasinglulu #define APPS_SMMU_QCOM (APPS_SMMU_BASE + 0xf0000) 25*91f16700Schasinglulu #define GPU_SMMU_BASE (PCNOC_BASE + 0x1f00000) 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define BLSP1_BASE (PCNOC_BASE + 0x7880000) 28*91f16700Schasinglulu #define BLSP1_UART_BASE(n) (BLSP1_BASE + 0x2f000 + (((n) - 1) * 0x1000)) 29*91f16700Schasinglulu #define BLSP_UART_BASE BLSP1_UART_BASE(QTI_UART_NUM) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define APCS_QGIC2_BASE (APCS_BASE + 0x00000) 32*91f16700Schasinglulu #define APCS_QGIC2_GICD (APCS_QGIC2_BASE + 0x0000) 33*91f16700Schasinglulu #define APCS_QGIC2_GICC (APCS_QGIC2_BASE + 0x2000) 34*91f16700Schasinglulu #define APCS_BANKED_ACS (APCS_BASE + 0x08000) 35*91f16700Schasinglulu #define APCS_BANKED_SAW2 (APCS_BASE + 0x09000) 36*91f16700Schasinglulu 37*91f16700Schasinglulu #define _APCS_CLUSTER(cluster) (APCS_BASE + ((cluster) * 0x100000)) 38*91f16700Schasinglulu #define _APCS_CPU(cluster, cpu) (_APCS_CLUSTER(cluster) + ((cpu) * 0x10000)) 39*91f16700Schasinglulu #define APCS_CFG(cluster) (_APCS_CLUSTER(cluster) + 0x10000) 40*91f16700Schasinglulu #define APCS_GLB(cluster) (_APCS_CLUSTER(cluster) + 0x11000) 41*91f16700Schasinglulu #define APCS_L2_SAW2(cluster) (_APCS_CLUSTER(cluster) + 0x12000) 42*91f16700Schasinglulu #define APCS_QTMR(cluster) (_APCS_CLUSTER(cluster) + 0x20000) 43*91f16700Schasinglulu #define APCS_ALIAS_ACS(cluster, cpu) (_APCS_CPU(cluster, cpu) + 0x88000) 44*91f16700Schasinglulu #define APCS_ALIAS_SAW2(cluster, cpu) (_APCS_CPU(cluster, cpu) + 0x89000) 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* Only on platforms with multiple clusters (e.g. MSM8939) */ 47*91f16700Schasinglulu #define APCS_CCI_BASE (APCS_BASE + 0x1c0000) 48*91f16700Schasinglulu #define APCS_CCI_SAW2 (APCS_BASE + 0x1d2000) 49*91f16700Schasinglulu #define APCS_CCI_ACS (APCS_BASE + 0x1d4000) 50*91f16700Schasinglulu 51*91f16700Schasinglulu #endif /* MSM8916_MMAP_H */ 52