1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, Google LLC. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <drivers/delay_timer.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <qti_plat.h> 10*91f16700Schasinglulu #include <spmi_arb.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* 13*91f16700Schasinglulu * This driver implements PON support for PM8998-compatible PMICs. This can 14*91f16700Schasinglulu * include other part numbers like PM6150. 15*91f16700Schasinglulu */ 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define RESET_TYPE_WARM_RESET 1 18*91f16700Schasinglulu #define RESET_TYPE_SHUTDOWN 4 19*91f16700Schasinglulu 20*91f16700Schasinglulu #define S2_RESET_EN BIT(7) 21*91f16700Schasinglulu 22*91f16700Schasinglulu static void configure_ps_hold(uint32_t reset_type) 23*91f16700Schasinglulu { 24*91f16700Schasinglulu /* QTI recommends disabling reset for 10 cycles before reconfiguring. */ 25*91f16700Schasinglulu spmi_arb_write8(PON_PS_HOLD_RESET_CTL2, 0); 26*91f16700Schasinglulu mdelay(1); 27*91f16700Schasinglulu 28*91f16700Schasinglulu spmi_arb_write8(PON_PS_HOLD_RESET_CTL, reset_type); 29*91f16700Schasinglulu spmi_arb_write8(PON_PS_HOLD_RESET_CTL2, S2_RESET_EN); 30*91f16700Schasinglulu mdelay(1); 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu void qti_pmic_prepare_reset(void) 34*91f16700Schasinglulu { 35*91f16700Schasinglulu configure_ps_hold(RESET_TYPE_WARM_RESET); 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu void qti_pmic_prepare_shutdown(void) 39*91f16700Schasinglulu { 40*91f16700Schasinglulu configure_ps_hold(RESET_TYPE_SHUTDOWN); 41*91f16700Schasinglulu } 42