xref: /arm-trusted-firmware/plat/qti/common/src/aarch64/qti_helpers.S (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu/*
2*91f16700Schasinglulu * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu * Copyright (c) 2018,2020, The Linux Foundation. All rights reserved.
4*91f16700Schasinglulu *
5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause
6*91f16700Schasinglulu */
7*91f16700Schasinglulu
8*91f16700Schasinglulu#include <arch.h>
9*91f16700Schasinglulu#include <asm_macros.S>
10*91f16700Schasinglulu#include <drivers/arm/gicv2.h>
11*91f16700Schasinglulu#include <drivers/arm/gicv3.h>
12*91f16700Schasinglulu#include <drivers/console.h>
13*91f16700Schasinglulu
14*91f16700Schasinglulu#include <platform_def.h>
15*91f16700Schasinglulu
16*91f16700Schasinglulu	.globl	plat_my_core_pos
17*91f16700Schasinglulu	.globl	plat_qti_core_pos_by_mpidr
18*91f16700Schasinglulu	.globl	plat_reset_handler
19*91f16700Schasinglulu	.globl	plat_panic_handler
20*91f16700Schasinglulu
21*91f16700Schasinglulu	/* -----------------------------------------------------
22*91f16700Schasinglulu	 *  unsigned int plat_qti_core_pos_by_mpidr(uint64_t mpidr)
23*91f16700Schasinglulu	 *  Helper function to calculate the core position.
24*91f16700Schasinglulu	 *  With this function:
25*91f16700Schasinglulu	 *  CorePos = (ClusterId * 4) + CoreId
26*91f16700Schasinglulu	 *  - In ARM v8   (MPIDR_EL1[24]=0)
27*91f16700Schasinglulu	 *    ClusterId = MPIDR_EL1[15:8]
28*91f16700Schasinglulu	 *    CoreId    = MPIDR_EL1[7:0]
29*91f16700Schasinglulu	 *  - In ARM v8.1 (MPIDR_EL1[24]=1)
30*91f16700Schasinglulu	 *    ClusterId = MPIDR_EL1[23:15]
31*91f16700Schasinglulu	 *    CoreId    = MPIDR_EL1[15:8]
32*91f16700Schasinglulu	 *  Clobbers: x0 & x1.
33*91f16700Schasinglulu	 * -----------------------------------------------------
34*91f16700Schasinglulu	 */
35*91f16700Schasinglulufunc plat_qti_core_pos_by_mpidr
36*91f16700Schasinglulu	mrs	x1, mpidr_el1
37*91f16700Schasinglulu	tst	x1, #MPIDR_MT_MASK
38*91f16700Schasinglulu	beq	plat_qti_core_pos_by_mpidr_no_mt
39*91f16700Schasinglulu	/* Right shift mpidr by one affinity level when MT=1. */
40*91f16700Schasinglulu	lsr	x0, x0, #MPIDR_AFFINITY_BITS
41*91f16700Schasingluluplat_qti_core_pos_by_mpidr_no_mt:
42*91f16700Schasinglulu	and	x1, x0, #MPIDR_CPU_MASK
43*91f16700Schasinglulu	and	x0, x0, #MPIDR_CLUSTER_MASK
44*91f16700Schasinglulu	add	x0, x1, x0, LSR #6
45*91f16700Schasinglulu	ret
46*91f16700Schasingluluendfunc plat_qti_core_pos_by_mpidr
47*91f16700Schasinglulu
48*91f16700Schasinglulu	/* --------------------------------------------------------------------
49*91f16700Schasinglulu	 * void plat_panic_handler(void)
50*91f16700Schasinglulu	 * calls SDI and reset system
51*91f16700Schasinglulu	 * --------------------------------------------------------------------
52*91f16700Schasinglulu	 */
53*91f16700Schasinglulufunc plat_panic_handler
54*91f16700Schasinglulu	msr	spsel, #0
55*91f16700Schasinglulu	bl	plat_set_my_stack
56*91f16700Schasinglulu	b	qtiseclib_panic
57*91f16700Schasingluluendfunc plat_panic_handler
58*91f16700Schasinglulu
59*91f16700Schasinglulu	/* -----------------------------------------------------
60*91f16700Schasinglulu	 *  unsigned int plat_my_core_pos(void)
61*91f16700Schasinglulu	 *  This function uses the plat_qti_calc_core_pos()
62*91f16700Schasinglulu	 *  definition to get the index of the calling CPU
63*91f16700Schasinglulu	 *  Clobbers: x0 & x1.
64*91f16700Schasinglulu	 * -----------------------------------------------------
65*91f16700Schasinglulu	 */
66*91f16700Schasinglulufunc plat_my_core_pos
67*91f16700Schasinglulu	mrs	x0, mpidr_el1
68*91f16700Schasinglulu	b	plat_qti_core_pos_by_mpidr
69*91f16700Schasingluluendfunc plat_my_core_pos
70*91f16700Schasinglulu
71*91f16700Schasinglulufunc plat_reset_handler
72*91f16700Schasinglulu	/* save the lr */
73*91f16700Schasinglulu	mov	x18, x30
74*91f16700Schasinglulu
75*91f16700Schasinglulu	/* pass cold boot status. */
76*91f16700Schasinglulu	ldr	w0, g_qti_bl31_cold_booted
77*91f16700Schasinglulu	/* Execuete CPUSS boot set up on every core. */
78*91f16700Schasinglulu	bl	qtiseclib_cpuss_reset_asm
79*91f16700Schasinglulu
80*91f16700Schasinglulu	ret	x18
81*91f16700Schasingluluendfunc plat_reset_handler
82