1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, Nuvia Inc 3*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <arch.h> 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu #include "sbsa_private.h" 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* The power domain tree descriptor */ 15*91f16700Schasinglulu static unsigned char power_domain_tree_desc[PLATFORM_CLUSTER_COUNT + 1]; 16*91f16700Schasinglulu 17*91f16700Schasinglulu /******************************************************************************* 18*91f16700Schasinglulu * This function returns the sbsa-ref default topology tree information. 19*91f16700Schasinglulu ******************************************************************************/ 20*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 21*91f16700Schasinglulu { 22*91f16700Schasinglulu unsigned int i; 23*91f16700Schasinglulu 24*91f16700Schasinglulu power_domain_tree_desc[0] = PLATFORM_CLUSTER_COUNT; 25*91f16700Schasinglulu 26*91f16700Schasinglulu for (i = 0U; i < PLATFORM_CLUSTER_COUNT; i++) { 27*91f16700Schasinglulu power_domain_tree_desc[i + 1] = PLATFORM_MAX_CPUS_PER_CLUSTER; 28*91f16700Schasinglulu } 29*91f16700Schasinglulu 30*91f16700Schasinglulu return power_domain_tree_desc; 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu /******************************************************************************* 34*91f16700Schasinglulu * This function implements a part of the critical interface between the psci 35*91f16700Schasinglulu * generic layer and the platform that allows the former to query the platform 36*91f16700Schasinglulu * to convert an MPIDR to a unique linear index. An error code (-1) is returned 37*91f16700Schasinglulu * in case the MPIDR is invalid. 38*91f16700Schasinglulu ******************************************************************************/ 39*91f16700Schasinglulu int plat_core_pos_by_mpidr(u_register_t mpidr) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu unsigned int cluster_id, cpu_id; 42*91f16700Schasinglulu 43*91f16700Schasinglulu mpidr &= MPIDR_AFFINITY_MASK; 44*91f16700Schasinglulu if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) { 45*91f16700Schasinglulu ERROR("Invalid MPIDR\n"); 46*91f16700Schasinglulu return -1; 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 50*91f16700Schasinglulu cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 51*91f16700Schasinglulu 52*91f16700Schasinglulu if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 53*91f16700Schasinglulu ERROR("cluster_id >= PLATFORM_CLUSTER_COUNT define\n"); 54*91f16700Schasinglulu return -1; 55*91f16700Schasinglulu } 56*91f16700Schasinglulu 57*91f16700Schasinglulu if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { 58*91f16700Schasinglulu ERROR("cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER define\n"); 59*91f16700Schasinglulu return -1; 60*91f16700Schasinglulu } 61*91f16700Schasinglulu 62*91f16700Schasinglulu return plat_qemu_calc_core_pos(mpidr); 63*91f16700Schasinglulu } 64