1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/bl_common.h> 10*91f16700Schasinglulu #include <drivers/arm/pl061_gpio.h> 11*91f16700Schasinglulu #include <plat/common/platform.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include "qemu_private.h" 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 16*91f16700Schasinglulu BL31_BASE, \ 17*91f16700Schasinglulu BL31_END - BL31_BASE, \ 18*91f16700Schasinglulu MT_MEMORY | MT_RW | EL3_PAS) 19*91f16700Schasinglulu #define MAP_BL31_RO MAP_REGION_FLAT( \ 20*91f16700Schasinglulu BL_CODE_BASE, \ 21*91f16700Schasinglulu BL_CODE_END - BL_CODE_BASE, \ 22*91f16700Schasinglulu MT_CODE | EL3_PAS), \ 23*91f16700Schasinglulu MAP_REGION_FLAT( \ 24*91f16700Schasinglulu BL_RO_DATA_BASE, \ 25*91f16700Schasinglulu BL_RO_DATA_END \ 26*91f16700Schasinglulu - BL_RO_DATA_BASE, \ 27*91f16700Schasinglulu MT_RO_DATA | EL3_PAS) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #if USE_COHERENT_MEM 30*91f16700Schasinglulu #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 31*91f16700Schasinglulu BL_COHERENT_RAM_BASE, \ 32*91f16700Schasinglulu BL_COHERENT_RAM_END \ 33*91f16700Schasinglulu - BL_COHERENT_RAM_BASE, \ 34*91f16700Schasinglulu MT_DEVICE | MT_RW | EL3_PAS) 35*91f16700Schasinglulu #endif 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* 38*91f16700Schasinglulu * Placeholder variables for copying the arguments that have been passed to 39*91f16700Schasinglulu * BL3-1 from BL2. 40*91f16700Schasinglulu */ 41*91f16700Schasinglulu static entry_point_info_t bl32_image_ep_info; 42*91f16700Schasinglulu static entry_point_info_t bl33_image_ep_info; 43*91f16700Schasinglulu 44*91f16700Schasinglulu /******************************************************************************* 45*91f16700Schasinglulu * Perform any BL3-1 early platform setup. Here is an opportunity to copy 46*91f16700Schasinglulu * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 47*91f16700Schasinglulu * they are lost (potentially). This needs to be done before the MMU is 48*91f16700Schasinglulu * initialized so that the memory layout can be used while creating page 49*91f16700Schasinglulu * tables. BL2 has flushed this information to memory, so we are guaranteed 50*91f16700Schasinglulu * to pick up good data. 51*91f16700Schasinglulu ******************************************************************************/ 52*91f16700Schasinglulu void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 53*91f16700Schasinglulu u_register_t arg2, u_register_t arg3) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu /* Initialize the console to provide early debug support */ 56*91f16700Schasinglulu qemu_console_init(); 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* Platform names have to be lowercase. */ 59*91f16700Schasinglulu #ifdef PLAT_qemu_sbsa 60*91f16700Schasinglulu sip_svc_init(); 61*91f16700Schasinglulu #endif 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* 64*91f16700Schasinglulu * Check params passed from BL2 65*91f16700Schasinglulu */ 66*91f16700Schasinglulu bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 67*91f16700Schasinglulu 68*91f16700Schasinglulu assert(params_from_bl2); 69*91f16700Schasinglulu assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 70*91f16700Schasinglulu assert(params_from_bl2->h.version >= VERSION_2); 71*91f16700Schasinglulu 72*91f16700Schasinglulu bl_params_node_t *bl_params = params_from_bl2->head; 73*91f16700Schasinglulu 74*91f16700Schasinglulu /* 75*91f16700Schasinglulu * Copy BL33 and BL32 (if present), entry point information. 76*91f16700Schasinglulu * They are stored in Secure RAM, in BL2's address space. 77*91f16700Schasinglulu */ 78*91f16700Schasinglulu while (bl_params) { 79*91f16700Schasinglulu if (bl_params->image_id == BL32_IMAGE_ID) 80*91f16700Schasinglulu bl32_image_ep_info = *bl_params->ep_info; 81*91f16700Schasinglulu 82*91f16700Schasinglulu if (bl_params->image_id == BL33_IMAGE_ID) 83*91f16700Schasinglulu bl33_image_ep_info = *bl_params->ep_info; 84*91f16700Schasinglulu 85*91f16700Schasinglulu bl_params = bl_params->next_params_info; 86*91f16700Schasinglulu } 87*91f16700Schasinglulu 88*91f16700Schasinglulu if (!bl33_image_ep_info.pc) 89*91f16700Schasinglulu panic(); 90*91f16700Schasinglulu } 91*91f16700Schasinglulu 92*91f16700Schasinglulu void bl31_plat_arch_setup(void) 93*91f16700Schasinglulu { 94*91f16700Schasinglulu const mmap_region_t bl_regions[] = { 95*91f16700Schasinglulu MAP_BL31_TOTAL, 96*91f16700Schasinglulu MAP_BL31_RO, 97*91f16700Schasinglulu #if USE_COHERENT_MEM 98*91f16700Schasinglulu MAP_BL_COHERENT_RAM, 99*91f16700Schasinglulu #endif 100*91f16700Schasinglulu {0} 101*91f16700Schasinglulu }; 102*91f16700Schasinglulu 103*91f16700Schasinglulu setup_page_tables(bl_regions, plat_qemu_get_mmap()); 104*91f16700Schasinglulu 105*91f16700Schasinglulu enable_mmu_el3(0); 106*91f16700Schasinglulu } 107*91f16700Schasinglulu 108*91f16700Schasinglulu static void qemu_gpio_init(void) 109*91f16700Schasinglulu { 110*91f16700Schasinglulu #ifdef SECURE_GPIO_BASE 111*91f16700Schasinglulu pl061_gpio_init(); 112*91f16700Schasinglulu pl061_gpio_register(SECURE_GPIO_BASE, 0); 113*91f16700Schasinglulu #endif 114*91f16700Schasinglulu } 115*91f16700Schasinglulu 116*91f16700Schasinglulu void bl31_platform_setup(void) 117*91f16700Schasinglulu { 118*91f16700Schasinglulu plat_qemu_gic_init(); 119*91f16700Schasinglulu qemu_gpio_init(); 120*91f16700Schasinglulu } 121*91f16700Schasinglulu 122*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 123*91f16700Schasinglulu { 124*91f16700Schasinglulu return SYS_COUNTER_FREQ_IN_TICKS; 125*91f16700Schasinglulu } 126*91f16700Schasinglulu 127*91f16700Schasinglulu /******************************************************************************* 128*91f16700Schasinglulu * Return a pointer to the 'entry_point_info' structure of the next image 129*91f16700Schasinglulu * for the security state specified. BL3-3 corresponds to the non-secure 130*91f16700Schasinglulu * image type while BL3-2 corresponds to the secure image type. A NULL 131*91f16700Schasinglulu * pointer is returned if the image does not exist. 132*91f16700Schasinglulu ******************************************************************************/ 133*91f16700Schasinglulu entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 134*91f16700Schasinglulu { 135*91f16700Schasinglulu entry_point_info_t *next_image_info; 136*91f16700Schasinglulu 137*91f16700Schasinglulu assert(sec_state_is_valid(type)); 138*91f16700Schasinglulu next_image_info = (type == NON_SECURE) 139*91f16700Schasinglulu ? &bl33_image_ep_info : &bl32_image_ep_info; 140*91f16700Schasinglulu /* 141*91f16700Schasinglulu * None of the images on the ARM development platforms can have 0x0 142*91f16700Schasinglulu * as the entrypoint 143*91f16700Schasinglulu */ 144*91f16700Schasinglulu if (next_image_info->pc) 145*91f16700Schasinglulu return next_image_info; 146*91f16700Schasinglulu else 147*91f16700Schasinglulu return NULL; 148*91f16700Schasinglulu } 149