1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <arch.h> 12*91f16700Schasinglulu #include <arch_helpers.h> 13*91f16700Schasinglulu #include <common/bl_common.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include "qemu_private.h" 16*91f16700Schasinglulu 17*91f16700Schasinglulu #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 18*91f16700Schasinglulu bl1_tzram_layout.total_base, \ 19*91f16700Schasinglulu bl1_tzram_layout.total_size, \ 20*91f16700Schasinglulu MT_MEMORY | MT_RW | EL3_PAS) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define MAP_BL1_RO MAP_REGION_FLAT( \ 23*91f16700Schasinglulu BL_CODE_BASE, \ 24*91f16700Schasinglulu BL1_CODE_END - BL_CODE_BASE, \ 25*91f16700Schasinglulu MT_CODE | EL3_PAS), \ 26*91f16700Schasinglulu MAP_REGION_FLAT( \ 27*91f16700Schasinglulu BL1_RO_DATA_BASE, \ 28*91f16700Schasinglulu BL1_RO_DATA_END \ 29*91f16700Schasinglulu - BL_RO_DATA_BASE, \ 30*91f16700Schasinglulu MT_RO_DATA | EL3_PAS) 31*91f16700Schasinglulu 32*91f16700Schasinglulu #if USE_COHERENT_MEM 33*91f16700Schasinglulu #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 34*91f16700Schasinglulu BL_COHERENT_RAM_BASE, \ 35*91f16700Schasinglulu BL_COHERENT_RAM_END \ 36*91f16700Schasinglulu - BL_COHERENT_RAM_BASE, \ 37*91f16700Schasinglulu MT_DEVICE | MT_RW | EL3_PAS) 38*91f16700Schasinglulu #endif 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* Data structure which holds the extents of the trusted SRAM for BL1*/ 41*91f16700Schasinglulu static meminfo_t bl1_tzram_layout; 42*91f16700Schasinglulu 43*91f16700Schasinglulu 44*91f16700Schasinglulu meminfo_t *bl1_plat_sec_mem_layout(void) 45*91f16700Schasinglulu { 46*91f16700Schasinglulu return &bl1_tzram_layout; 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu /******************************************************************************* 50*91f16700Schasinglulu * Perform any BL1 specific platform actions. 51*91f16700Schasinglulu ******************************************************************************/ 52*91f16700Schasinglulu void bl1_early_platform_setup(void) 53*91f16700Schasinglulu { 54*91f16700Schasinglulu /* Initialize the console to provide early debug support */ 55*91f16700Schasinglulu qemu_console_init(); 56*91f16700Schasinglulu 57*91f16700Schasinglulu /* Allow BL1 to see the whole Trusted RAM */ 58*91f16700Schasinglulu bl1_tzram_layout.total_base = BL_RAM_BASE; 59*91f16700Schasinglulu bl1_tzram_layout.total_size = BL_RAM_SIZE; 60*91f16700Schasinglulu } 61*91f16700Schasinglulu 62*91f16700Schasinglulu /****************************************************************************** 63*91f16700Schasinglulu * Perform the very early platform specific architecture setup. This only 64*91f16700Schasinglulu * does basic initialization. Later architectural setup (bl1_arch_setup()) 65*91f16700Schasinglulu * does not do anything platform specific. 66*91f16700Schasinglulu *****************************************************************************/ 67*91f16700Schasinglulu #ifdef __aarch64__ 68*91f16700Schasinglulu #define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__) 69*91f16700Schasinglulu #else 70*91f16700Schasinglulu #define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) 71*91f16700Schasinglulu #endif 72*91f16700Schasinglulu 73*91f16700Schasinglulu void bl1_plat_arch_setup(void) 74*91f16700Schasinglulu { 75*91f16700Schasinglulu const mmap_region_t bl_regions[] = { 76*91f16700Schasinglulu MAP_BL1_TOTAL, 77*91f16700Schasinglulu MAP_BL1_RO, 78*91f16700Schasinglulu #if USE_COHERENT_MEM 79*91f16700Schasinglulu MAP_BL_COHERENT_RAM, 80*91f16700Schasinglulu #endif 81*91f16700Schasinglulu {0} 82*91f16700Schasinglulu }; 83*91f16700Schasinglulu 84*91f16700Schasinglulu setup_page_tables(bl_regions, plat_qemu_get_mmap()); 85*91f16700Schasinglulu #ifdef __aarch64__ 86*91f16700Schasinglulu enable_mmu_el3(0); 87*91f16700Schasinglulu #else 88*91f16700Schasinglulu enable_mmu_svc_mon(0); 89*91f16700Schasinglulu #endif 90*91f16700Schasinglulu } 91*91f16700Schasinglulu 92*91f16700Schasinglulu void bl1_platform_setup(void) 93*91f16700Schasinglulu { 94*91f16700Schasinglulu plat_qemu_io_setup(); 95*91f16700Schasinglulu } 96