1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <assert_macros.S> 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .globl plat_my_core_pos 13*91f16700Schasinglulu .globl plat_get_my_entrypoint 14*91f16700Schasinglulu .globl platform_mem_init 15*91f16700Schasinglulu .globl plat_qemu_calc_core_pos 16*91f16700Schasinglulu .globl plat_crash_console_init 17*91f16700Schasinglulu .globl plat_crash_console_putc 18*91f16700Schasinglulu .globl plat_crash_console_flush 19*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 20*91f16700Schasinglulu .globl plat_get_my_entrypoint 21*91f16700Schasinglulu .globl plat_is_my_cpu_primary 22*91f16700Schasinglulu 23*91f16700Schasinglulufunc plat_my_core_pos 24*91f16700Schasinglulu mrs x0, mpidr_el1 25*91f16700Schasinglulu b plat_qemu_calc_core_pos 26*91f16700Schasingluluendfunc plat_my_core_pos 27*91f16700Schasinglulu 28*91f16700Schasinglulu/* 29*91f16700Schasinglulu * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); 30*91f16700Schasinglulu * With this function: CorePos = (ClusterId * 4) + CoreId 31*91f16700Schasinglulu */ 32*91f16700Schasinglulufunc plat_qemu_calc_core_pos 33*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 34*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 35*91f16700Schasinglulu add x0, x1, x0, LSR #(MPIDR_AFFINITY_BITS -\ 36*91f16700Schasinglulu PLATFORM_CPU_PER_CLUSTER_SHIFT) 37*91f16700Schasinglulu ret 38*91f16700Schasingluluendfunc plat_qemu_calc_core_pos 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* ----------------------------------------------------- 41*91f16700Schasinglulu * unsigned int plat_is_my_cpu_primary (void); 42*91f16700Schasinglulu * 43*91f16700Schasinglulu * Find out whether the current cpu is the primary 44*91f16700Schasinglulu * cpu. 45*91f16700Schasinglulu * ----------------------------------------------------- 46*91f16700Schasinglulu */ 47*91f16700Schasinglulufunc plat_is_my_cpu_primary 48*91f16700Schasinglulu mrs x0, mpidr_el1 49*91f16700Schasinglulu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 50*91f16700Schasinglulu cmp x0, #QEMU_PRIMARY_CPU 51*91f16700Schasinglulu cset w0, eq 52*91f16700Schasinglulu ret 53*91f16700Schasingluluendfunc plat_is_my_cpu_primary 54*91f16700Schasinglulu 55*91f16700Schasinglulu /* ----------------------------------------------------- 56*91f16700Schasinglulu * void plat_secondary_cold_boot_setup (void); 57*91f16700Schasinglulu * 58*91f16700Schasinglulu * This function performs any platform specific actions 59*91f16700Schasinglulu * needed for a secondary cpu after a cold reset e.g 60*91f16700Schasinglulu * mark the cpu's presence, mechanism to place it in a 61*91f16700Schasinglulu * holding pen etc. 62*91f16700Schasinglulu * ----------------------------------------------------- 63*91f16700Schasinglulu */ 64*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 65*91f16700Schasinglulu /* Calculate address of our hold entry */ 66*91f16700Schasinglulu bl plat_my_core_pos 67*91f16700Schasinglulu lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT 68*91f16700Schasinglulu mov_imm x2, PLAT_QEMU_HOLD_BASE 69*91f16700Schasinglulu 70*91f16700Schasinglulu /* Wait until we have a go */ 71*91f16700Schasinglulupoll_mailbox: 72*91f16700Schasinglulu ldr x1, [x2, x0] 73*91f16700Schasinglulu cbz x1, 1f 74*91f16700Schasinglulu 75*91f16700Schasinglulu /* Clear the mailbox again ready for next time. */ 76*91f16700Schasinglulu mov x1, #PLAT_QEMU_HOLD_STATE_WAIT 77*91f16700Schasinglulu str x1, [x2, x0] 78*91f16700Schasinglulu 79*91f16700Schasinglulu /* Jump to the provided entrypoint. */ 80*91f16700Schasinglulu mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE 81*91f16700Schasinglulu ldr x1, [x0] 82*91f16700Schasinglulu br x1 83*91f16700Schasinglulu1: 84*91f16700Schasinglulu wfe 85*91f16700Schasinglulu b poll_mailbox 86*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 87*91f16700Schasinglulu 88*91f16700Schasinglulufunc plat_get_my_entrypoint 89*91f16700Schasinglulu /* TODO support warm boot */ 90*91f16700Schasinglulu mov x0, #0 91*91f16700Schasinglulu ret 92*91f16700Schasingluluendfunc plat_get_my_entrypoint 93*91f16700Schasinglulu 94*91f16700Schasinglulufunc platform_mem_init 95*91f16700Schasinglulu ret 96*91f16700Schasingluluendfunc platform_mem_init 97*91f16700Schasinglulu 98*91f16700Schasinglulu /* --------------------------------------------- 99*91f16700Schasinglulu * int plat_crash_console_init(void) 100*91f16700Schasinglulu * Function to initialize the crash console 101*91f16700Schasinglulu * without a C Runtime to print crash report. 102*91f16700Schasinglulu * Clobber list : x0, x1, x2 103*91f16700Schasinglulu * --------------------------------------------- 104*91f16700Schasinglulu */ 105*91f16700Schasinglulufunc plat_crash_console_init 106*91f16700Schasinglulu mov_imm x0, PLAT_QEMU_CRASH_UART_BASE 107*91f16700Schasinglulu mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ 108*91f16700Schasinglulu mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE 109*91f16700Schasinglulu b console_pl011_core_init 110*91f16700Schasingluluendfunc plat_crash_console_init 111*91f16700Schasinglulu 112*91f16700Schasinglulu /* --------------------------------------------- 113*91f16700Schasinglulu * int plat_crash_console_putc(int c) 114*91f16700Schasinglulu * Function to print a character on the crash 115*91f16700Schasinglulu * console without a C Runtime. 116*91f16700Schasinglulu * Clobber list : x1, x2 117*91f16700Schasinglulu * --------------------------------------------- 118*91f16700Schasinglulu */ 119*91f16700Schasinglulufunc plat_crash_console_putc 120*91f16700Schasinglulu mov_imm x1, PLAT_QEMU_CRASH_UART_BASE 121*91f16700Schasinglulu b console_pl011_core_putc 122*91f16700Schasingluluendfunc plat_crash_console_putc 123*91f16700Schasinglulu 124*91f16700Schasinglulu /* --------------------------------------------- 125*91f16700Schasinglulu * void plat_crash_console_flush(int c) 126*91f16700Schasinglulu * Function to force a write of all buffered 127*91f16700Schasinglulu * data that hasn't been output. 128*91f16700Schasinglulu * Out : void. 129*91f16700Schasinglulu * Clobber list : x0, x1 130*91f16700Schasinglulu * --------------------------------------------- 131*91f16700Schasinglulu */ 132*91f16700Schasinglulufunc plat_crash_console_flush 133*91f16700Schasinglulu mov_imm x0, PLAT_QEMU_CRASH_UART_BASE 134*91f16700Schasinglulu b console_pl011_core_flush 135*91f16700Schasingluluendfunc plat_crash_console_flush 136*91f16700Schasinglulu 137