1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc. 3*91f16700Schasinglulu# Copyright 2017-2022 NXP Semiconductors 4*91f16700Schasinglulu# 5*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu# 7*91f16700Schasinglulu# 8*91f16700Schasinglulu#------------------------------------------------------------------------------ 9*91f16700Schasinglulu# 10*91f16700Schasinglulu# This file contains the basic architecture definitions that drive the build 11*91f16700Schasinglulu# 12*91f16700Schasinglulu# ----------------------------------------------------------------------------- 13*91f16700Schasinglulu 14*91f16700SchasingluluCORE_TYPE := a72 15*91f16700Schasinglulu 16*91f16700SchasingluluCACHE_LINE := 6 17*91f16700Schasinglulu 18*91f16700Schasinglulu# set to GIC400 or GIC500 19*91f16700SchasingluluGIC := GIC500 20*91f16700Schasinglulu 21*91f16700Schasinglulu# set to CCI400 or CCN504 or CCN508 22*91f16700SchasingluluINTERCONNECT := CCN508 23*91f16700Schasinglulu 24*91f16700Schasinglulu# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 25*91f16700SchasingluluCHASSIS := 3_2 26*91f16700Schasinglulu 27*91f16700Schasinglulu# TZC IP Details TZC used is TZC380 or TZC400 28*91f16700SchasingluluTZC_ID := TZC400 29*91f16700Schasinglulu 30*91f16700Schasinglulu# CONSOLE Details available is NS16550 or PL011 31*91f16700SchasingluluCONSOLE := PL011 32*91f16700Schasinglulu 33*91f16700Schasinglulu# Select the DDR PHY generation to be used 34*91f16700SchasingluluPLAT_DDR_PHY := PHY_GEN2 35*91f16700Schasinglulu 36*91f16700SchasingluluPHYS_SYS := 64 37*91f16700Schasinglulu 38*91f16700Schasinglulu# Area of OCRAM reserved by ROM code 39*91f16700SchasingluluNXP_ROM_RSVD := 0xa000 40*91f16700Schasinglulu 41*91f16700Schasinglulu# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 42*91f16700Schasinglulu# Input to CST create_hdr_esbc tool 43*91f16700SchasingluluCSF_HDR_SZ := 0x3000 44*91f16700Schasinglulu 45*91f16700SchasingluluNXP_SFP_VER := 3_4 46*91f16700Schasinglulu 47*91f16700Schasinglulu# In IMAGE_BL2, compile time flag for handling Cache coherency 48*91f16700Schasinglulu# with CAAM for BL2 running from OCRAM 49*91f16700SchasingluluSEC_MEM_NON_COHERENT := yes 50*91f16700Schasinglulu 51*91f16700Schasinglulu# Defining the endianness for NXP ESDHC 52*91f16700SchasingluluNXP_ESDHC_ENDIANNESS := LE 53*91f16700Schasinglulu 54*91f16700Schasinglulu# Defining the endianness for NXP SFP 55*91f16700SchasingluluNXP_SFP_ENDIANNESS := LE 56*91f16700Schasinglulu 57*91f16700Schasinglulu# Defining the endianness for NXP GPIO 58*91f16700SchasingluluNXP_GPIO_ENDIANNESS := LE 59*91f16700Schasinglulu 60*91f16700Schasinglulu# Defining the endianness for NXP SNVS 61*91f16700SchasingluluNXP_SNVS_ENDIANNESS := LE 62*91f16700Schasinglulu 63*91f16700Schasinglulu# Defining the endianness for NXP CCSR GUR register 64*91f16700SchasingluluNXP_GUR_ENDIANNESS := LE 65*91f16700Schasinglulu 66*91f16700Schasinglulu# Defining the endianness for NXP FSPI register 67*91f16700SchasingluluNXP_FSPI_ENDIANNESS := LE 68*91f16700Schasinglulu 69*91f16700Schasinglulu# Defining the endianness for NXP SEC 70*91f16700SchasingluluNXP_SEC_ENDIANNESS := LE 71*91f16700Schasinglulu 72*91f16700Schasinglulu# Defining the endianness for NXP DDR 73*91f16700SchasingluluNXP_DDR_ENDIANNESS := LE 74*91f16700Schasinglulu 75*91f16700SchasingluluNXP_DDR_INTLV_256B := 1 76*91f16700Schasinglulu 77*91f16700Schasinglulu# OCRAM MAP for BL2 78*91f16700Schasinglulu# Before BL2 79*91f16700Schasinglulu# 0x18000000 - 0x18009fff -> Used by ROM code 80*91f16700Schasinglulu# 0x1800a000 - 0x1800dfff -> CSF header for BL2 81*91f16700Schasinglulu# (The above area i.e 0x18000000 - 0x1800dfff is available 82*91f16700Schasinglulu# for DDR PHY images scratch pad region during BL2 run time) 83*91f16700Schasinglulu# For FlexSPI boot 84*91f16700Schasinglulu# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary 85*91f16700Schasinglulu# For SD boot 86*91f16700Schasinglulu# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary 87*91f16700Schasinglulu# 0x18030000 - 0x18040000 -> Reserved for SD buffer 88*91f16700SchasingluluOCRAM_START_ADDR := 0x18000000 89*91f16700SchasingluluOCRAM_SIZE := 0x40000 90*91f16700Schasinglulu 91*91f16700Schasinglulu# Location of BL2 on OCRAM 92*91f16700SchasingluluBL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) 93*91f16700Schasinglulu# Covert to HEX to be used by create_pbl.mk 94*91f16700SchasingluluBL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) 95*91f16700Schasinglulu 96*91f16700Schasinglulu# BL2_HDR_LOC is at (OCRAM_ADDR + NXP_ROM_RSVD) 97*91f16700Schasinglulu# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE 98*91f16700SchasingluluBL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) ))) 99*91f16700Schasinglulu# Covert to HEX to be used by create_pbl.mk 100*91f16700SchasingluluBL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc) 101*91f16700Schasinglulu 102*91f16700Schasinglulu# SoC ERRATAS to be enabled 103*91f16700Schasinglulu# 104*91f16700Schasinglulu# Core Errata 105*91f16700SchasingluluERRATA_A72_859971 := 1 106*91f16700Schasinglulu 107*91f16700Schasinglulu# SoC Errata 108*91f16700SchasingluluERRATA_SOC_A050426 := 1 109*91f16700Schasinglulu 110*91f16700Schasinglulu# DDR Errata 111*91f16700SchasingluluERRATA_DDR_A011396 := 1 112*91f16700SchasingluluERRATA_DDR_A050450 := 1 113*91f16700SchasingluluERRATA_DDR_A050958 := 1 114*91f16700Schasinglulu 115*91f16700Schasinglulu# enable dynamic memory mapping 116*91f16700SchasingluluPLAT_XLAT_TABLES_DYNAMIC := 1 117*91f16700Schasinglulu 118*91f16700Schasinglulu# OCRAM ECC Enabled 119*91f16700SchasingluluOCRAM_ECC_EN := yes 120