1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PLAT_DEF_H 9*91f16700Schasinglulu #define PLAT_DEF_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <arch.h> 12*91f16700Schasinglulu #include <cortex_a72.h> 13*91f16700Schasinglulu /* Required without TBBR. 14*91f16700Schasinglulu * To include the defines for DDR PHY 15*91f16700Schasinglulu * Images. 16*91f16700Schasinglulu */ 17*91f16700Schasinglulu #include <tbbr_img_def.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu #include <policy.h> 20*91f16700Schasinglulu #include <soc.h> 21*91f16700Schasinglulu 22*91f16700Schasinglulu #if defined(IMAGE_BL31) 23*91f16700Schasinglulu #define LS_SYS_TIMCTL_BASE 0x2890000 24*91f16700Schasinglulu #define PLAT_LS_NSTIMER_FRAME_ID 0 25*91f16700Schasinglulu #define LS_CONFIG_CNTACR 1 26*91f16700Schasinglulu #endif 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define NXP_SYSCLK_FREQ 100000000 29*91f16700Schasinglulu #define NXP_DDRCLK_FREQ 100000000 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* UART related definition */ 32*91f16700Schasinglulu #define NXP_CONSOLE_ADDR NXP_UART_ADDR 33*91f16700Schasinglulu #define NXP_CONSOLE_BAUDRATE 115200 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* Size of cacheable stacks */ 36*91f16700Schasinglulu #if defined(IMAGE_BL2) 37*91f16700Schasinglulu #if defined(TRUSTED_BOARD_BOOT) 38*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x2000 39*91f16700Schasinglulu #else 40*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x1000 41*91f16700Schasinglulu #endif 42*91f16700Schasinglulu #elif defined(IMAGE_BL31) 43*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x1000 44*91f16700Schasinglulu #endif 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* SD block buffer */ 47*91f16700Schasinglulu #define NXP_SD_BLOCK_BUF_SIZE (0x8000) 48*91f16700Schasinglulu #define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 49*91f16700Schasinglulu - NXP_SD_BLOCK_BUF_SIZE) 50*91f16700Schasinglulu 51*91f16700Schasinglulu #ifdef SD_BOOT 52*91f16700Schasinglulu #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 53*91f16700Schasinglulu - NXP_SD_BLOCK_BUF_SIZE) 54*91f16700Schasinglulu #else 55*91f16700Schasinglulu #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 56*91f16700Schasinglulu #endif 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* IO defines as needed by IO driver framework */ 59*91f16700Schasinglulu #define MAX_IO_DEVICES 4 60*91f16700Schasinglulu #define MAX_IO_BLOCK_DEVICES 1 61*91f16700Schasinglulu #define MAX_IO_HANDLES 4 62*91f16700Schasinglulu 63*91f16700Schasinglulu #define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* 66*91f16700Schasinglulu * FIP image defines - Offset at which FIP Image would be present 67*91f16700Schasinglulu * Image would include Bl31 , Bl33 and Bl32 (optional) 68*91f16700Schasinglulu */ 69*91f16700Schasinglulu #ifdef POLICY_FUSE_PROVISION 70*91f16700Schasinglulu #define MAX_FIP_DEVICES 3 71*91f16700Schasinglulu #endif 72*91f16700Schasinglulu 73*91f16700Schasinglulu #ifndef MAX_FIP_DEVICES 74*91f16700Schasinglulu #define MAX_FIP_DEVICES 2 75*91f16700Schasinglulu #endif 76*91f16700Schasinglulu 77*91f16700Schasinglulu /* 78*91f16700Schasinglulu * ID of the secure physical generic timer interrupt used by the BL32. 79*91f16700Schasinglulu */ 80*91f16700Schasinglulu #define BL32_IRQ_SEC_PHY_TIMER 29 81*91f16700Schasinglulu 82*91f16700Schasinglulu #define BL31_WDOG_SEC 89 83*91f16700Schasinglulu 84*91f16700Schasinglulu #define BL31_NS_WDOG_WS1 108 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* 87*91f16700Schasinglulu * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 88*91f16700Schasinglulu * terminology. On a GICv2 system or mode, the lists will be merged and treated 89*91f16700Schasinglulu * as Group 0 interrupts. 90*91f16700Schasinglulu */ 91*91f16700Schasinglulu #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 92*91f16700Schasinglulu INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 93*91f16700Schasinglulu GIC_INTR_CFG_EDGE) 94*91f16700Schasinglulu 95*91f16700Schasinglulu /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 96*91f16700Schasinglulu #define NXP_IRQ_SEC_SGI_7 15 97*91f16700Schasinglulu 98*91f16700Schasinglulu #define PLAT_LS_G0_IRQ_PROPS(grp) \ 99*91f16700Schasinglulu INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 100*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 101*91f16700Schasinglulu INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 102*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 103*91f16700Schasinglulu INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 104*91f16700Schasinglulu GIC_INTR_CFG_LEVEL) 105*91f16700Schasinglulu #endif 106