1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright 2022 NXP 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu# 7*91f16700Schasinglulu#------------------------------------------------------------------------------ 8*91f16700Schasinglulu# 9*91f16700Schasinglulu# This file contains the basic architecture definitions that drive the build 10*91f16700Schasinglulu# 11*91f16700Schasinglulu# ----------------------------------------------------------------------------- 12*91f16700Schasinglulu 13*91f16700SchasingluluCORE_TYPE := a53 14*91f16700Schasinglulu 15*91f16700SchasingluluCACHE_LINE := 6 16*91f16700Schasinglulu 17*91f16700Schasinglulu# Set to GIC400 or GIC500 18*91f16700SchasingluluGIC := GIC500 19*91f16700Schasinglulu 20*91f16700Schasinglulu# Set to CCI400 or CCN504 or CCN508 21*91f16700SchasingluluINTERCONNECT := CCI400 22*91f16700Schasinglulu 23*91f16700Schasinglulu# Select the DDR PHY generation to be used 24*91f16700SchasingluluPLAT_DDR_PHY := PHY_GEN1 25*91f16700Schasinglulu 26*91f16700SchasingluluPHYS_SYS := 64 27*91f16700Schasinglulu 28*91f16700Schasinglulu# Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 29*91f16700SchasingluluCHASSIS := 3 30*91f16700Schasinglulu 31*91f16700Schasinglulu# TZC IP Details TZC used is TZC380 or TZC400 32*91f16700SchasingluluTZC_ID := TZC400 33*91f16700Schasinglulu 34*91f16700Schasinglulu# CONSOLE Details available is NS16550 or PL011 35*91f16700SchasingluluCONSOLE := NS16550 36*91f16700Schasinglulu 37*91f16700SchasingluluNXP_SFP_VER := 3_4 38*91f16700Schasinglulu 39*91f16700Schasinglulu# In IMAGE_BL2, compile time flag for handling Cache coherency 40*91f16700Schasinglulu# with CAAM for BL2 running from OCRAM 41*91f16700SchasingluluSEC_MEM_NON_COHERENT := yes 42*91f16700Schasinglulu 43*91f16700Schasinglulu 44*91f16700Schasinglulu# OCRAM MAP for BL2 45*91f16700Schasinglulu# Before BL2 46*91f16700Schasinglulu# 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables) 47*91f16700Schasinglulu# 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB) 48*91f16700Schasinglulu# 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB) 49*91f16700SchasingluluOCRAM_START_ADDR := 0x18000000 50*91f16700SchasingluluOCRAM_SIZE := 0x20000 51*91f16700Schasinglulu 52*91f16700SchasingluluCSF_HDR_SZ := 0x3000 53*91f16700Schasinglulu 54*91f16700Schasinglulu# Area of OCRAM reserved by ROM code 55*91f16700SchasingluluNXP_ROM_RSVD := 0xa000 56*91f16700Schasinglulu 57*91f16700Schasinglulu# Input to CST create_hdr_isbc tool 58*91f16700SchasingluluBL2_HDR_LOC := 0x1801D000 59*91f16700Schasinglulu 60*91f16700Schasinglulu# Location of BL2 on OCRAM 61*91f16700Schasinglulu# BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD 62*91f16700SchasingluluBL2_BASE := 0x1800a000 63*91f16700Schasinglulu 64*91f16700Schasinglulu# SoC ERRATUM to be enabled 65*91f16700Schasinglulu 66*91f16700Schasinglulu# ARM Erratum 67*91f16700SchasingluluERRATA_A53_855873 := 1 68*91f16700Schasinglulu 69*91f16700Schasinglulu# DDR Erratum 70*91f16700SchasingluluERRATA_DDR_A008511 := 1 71*91f16700SchasingluluERRATA_DDR_A009803 := 1 72*91f16700SchasingluluERRATA_DDR_A009942 := 1 73*91f16700SchasingluluERRATA_DDR_A010165 := 1 74*91f16700Schasinglulu 75*91f16700Schasinglulu# Define Endianness of each module 76*91f16700SchasingluluNXP_ESDHC_ENDIANNESS := LE 77*91f16700SchasingluluNXP_SFP_ENDIANNESS := LE 78*91f16700SchasingluluNXP_GPIO_ENDIANNESS := LE 79*91f16700SchasingluluNXP_SNVS_ENDIANNESS := LE 80*91f16700SchasingluluNXP_GUR_ENDIANNESS := LE 81*91f16700SchasingluluNXP_SEC_ENDIANNESS := LE 82*91f16700SchasingluluNXP_DDR_ENDIANNESS := LE 83*91f16700SchasingluluNXP_QSPI_ENDIANNESS := LE 84*91f16700Schasinglulu 85*91f16700Schasinglulu# OCRAM ECC Enabled 86*91f16700SchasingluluOCRAM_ECC_EN := yes 87