1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_DEF_H 8*91f16700Schasinglulu #define PLAT_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu /* 12*91f16700Schasinglulu * Required without TBBR. 13*91f16700Schasinglulu * To include the defines for DDR PHY 14*91f16700Schasinglulu * Images. 15*91f16700Schasinglulu */ 16*91f16700Schasinglulu #include <tbbr_img_def.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu #include <policy.h> 19*91f16700Schasinglulu #include <soc.h> 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define NXP_SPD_EEPROM0 0x51 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define NXP_SYSCLK_FREQ 100000000 24*91f16700Schasinglulu #define NXP_DDRCLK_FREQ 100000000 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* UART related definition */ 27*91f16700Schasinglulu #define NXP_CONSOLE_ADDR NXP_UART_ADDR 28*91f16700Schasinglulu #define NXP_CONSOLE_BAUDRATE 115200 29*91f16700Schasinglulu 30*91f16700Schasinglulu /* Size of cacheable stacks */ 31*91f16700Schasinglulu #if defined(IMAGE_BL2) 32*91f16700Schasinglulu #if defined(TRUSTED_BOARD_BOOT) 33*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x2000 34*91f16700Schasinglulu #else 35*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x1000 36*91f16700Schasinglulu #endif 37*91f16700Schasinglulu #elif defined(IMAGE_BL31) 38*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x1000 39*91f16700Schasinglulu #endif 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define BL2_START NXP_OCRAM_ADDR 42*91f16700Schasinglulu #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 43*91f16700Schasinglulu #define BL2_NOLOAD_START NXP_OCRAM_ADDR 44*91f16700Schasinglulu #define BL2_NOLOAD_LIMIT BL2_BASE 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* IO defines as needed by IO driver framework */ 47*91f16700Schasinglulu #define MAX_IO_DEVICES 4 48*91f16700Schasinglulu #define MAX_IO_BLOCK_DEVICES 1 49*91f16700Schasinglulu #define MAX_IO_HANDLES 4 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* 52*91f16700Schasinglulu * FIP image defines - Offset at which FIP Image would be present 53*91f16700Schasinglulu * Image would include Bl31 , Bl33 and Bl32 (optional) 54*91f16700Schasinglulu */ 55*91f16700Schasinglulu #ifdef POLICY_FUSE_PROVISION 56*91f16700Schasinglulu #define MAX_FIP_DEVICES 2 57*91f16700Schasinglulu #endif 58*91f16700Schasinglulu 59*91f16700Schasinglulu #ifndef MAX_FIP_DEVICES 60*91f16700Schasinglulu #define MAX_FIP_DEVICES 1 61*91f16700Schasinglulu #endif 62*91f16700Schasinglulu 63*91f16700Schasinglulu #define BL32_IRQ_SEC_PHY_TIMER 29 64*91f16700Schasinglulu #define BL31_WDOG_SEC 89 65*91f16700Schasinglulu 66*91f16700Schasinglulu /* 67*91f16700Schasinglulu * ID of the secure physical generic timer interrupt used by the BL32. 68*91f16700Schasinglulu */ 69*91f16700Schasinglulu #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 70*91f16700Schasinglulu INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 71*91f16700Schasinglulu GIC_INTR_CFG_LEVEL) 72*91f16700Schasinglulu 73*91f16700Schasinglulu /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 74*91f16700Schasinglulu #define PLAT_LS_G0_IRQ_PROPS(grp) \ 75*91f16700Schasinglulu INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 76*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 77*91f16700Schasinglulu INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ 78*91f16700Schasinglulu GIC_INTR_CFG_LEVEL) 79*91f16700Schasinglulu 80*91f16700Schasinglulu 81*91f16700Schasinglulu #endif /* PLAT_DEF_H */ 82