1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <errno.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <ddr.h> 11*91f16700Schasinglulu #include <utils.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <errata.h> 14*91f16700Schasinglulu #include <platform_def.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #ifdef CONFIG_STATIC_DDR 17*91f16700Schasinglulu #error No static value defined 18*91f16700Schasinglulu #endif 19*91f16700Schasinglulu 20*91f16700Schasinglulu static const struct rc_timing rce[] = { 21*91f16700Schasinglulu {U(1600), U(8), U(8)}, 22*91f16700Schasinglulu {U(1867), U(8), U(8)}, 23*91f16700Schasinglulu {U(2134), U(8), U(9)}, 24*91f16700Schasinglulu {} 25*91f16700Schasinglulu }; 26*91f16700Schasinglulu 27*91f16700Schasinglulu static const struct board_timing udimm[] = { 28*91f16700Schasinglulu {U(0x04), rce, U(0x01020307), U(0x08090b06)}, 29*91f16700Schasinglulu }; 30*91f16700Schasinglulu 31*91f16700Schasinglulu int ddr_board_options(struct ddr_info *priv) 32*91f16700Schasinglulu { 33*91f16700Schasinglulu int ret; 34*91f16700Schasinglulu struct memctl_opt *popts = &priv->opt; 35*91f16700Schasinglulu 36*91f16700Schasinglulu if (popts->rdimm != 0) { 37*91f16700Schasinglulu debug("RDIMM parameters not set.\n"); 38*91f16700Schasinglulu return -EINVAL; 39*91f16700Schasinglulu } 40*91f16700Schasinglulu 41*91f16700Schasinglulu ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm)); 42*91f16700Schasinglulu if (ret != 0) { 43*91f16700Schasinglulu return ret; 44*91f16700Schasinglulu } 45*91f16700Schasinglulu 46*91f16700Schasinglulu popts->addr_hash = 1; 47*91f16700Schasinglulu popts->cpo_sample = U(0x7b); 48*91f16700Schasinglulu popts->ddr_cdr1 = DDR_CDR1_DHC_EN | 49*91f16700Schasinglulu DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); 50*91f16700Schasinglulu popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | 51*91f16700Schasinglulu DDR_CDR2_VREF_TRAIN_EN | 52*91f16700Schasinglulu DDR_CDR2_VREF_RANGE_2; 53*91f16700Schasinglulu 54*91f16700Schasinglulu return 0; 55*91f16700Schasinglulu } 56*91f16700Schasinglulu 57*91f16700Schasinglulu long long init_ddr(void) 58*91f16700Schasinglulu { 59*91f16700Schasinglulu int spd_addr[] = { NXP_SPD_EEPROM0 }; 60*91f16700Schasinglulu struct ddr_info info; 61*91f16700Schasinglulu struct sysinfo sys; 62*91f16700Schasinglulu long long dram_size; 63*91f16700Schasinglulu 64*91f16700Schasinglulu zeromem(&sys, sizeof(sys)); 65*91f16700Schasinglulu get_clocks(&sys); 66*91f16700Schasinglulu debug("platform clock %lu\n", sys.freq_platform); 67*91f16700Schasinglulu debug("DDR PLL %lu\n", sys.freq_ddr_pll0); 68*91f16700Schasinglulu 69*91f16700Schasinglulu zeromem(&info, sizeof(struct ddr_info)); 70*91f16700Schasinglulu info.num_ctlrs = NUM_OF_DDRC; 71*91f16700Schasinglulu info.dimm_on_ctlr = DDRC_NUM_DIMM; 72*91f16700Schasinglulu info.clk = get_ddr_freq(&sys, 0); 73*91f16700Schasinglulu info.spd_addr = spd_addr; 74*91f16700Schasinglulu info.ddr[0] = (void *)NXP_DDR_ADDR; 75*91f16700Schasinglulu 76*91f16700Schasinglulu dram_size = dram_init(&info); 77*91f16700Schasinglulu if (dram_size < 0) { 78*91f16700Schasinglulu ERROR("DDR init failed.\n"); 79*91f16700Schasinglulu } 80*91f16700Schasinglulu 81*91f16700Schasinglulu return dram_size; 82*91f16700Schasinglulu } 83