1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright 2022 NXP 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu# 7*91f16700Schasinglulu#------------------------------------------------------------------------------ 8*91f16700Schasinglulu# 9*91f16700Schasinglulu# This file contains the basic architecture definitions that drive the build 10*91f16700Schasinglulu# 11*91f16700Schasinglulu# ----------------------------------------------------------------------------- 12*91f16700Schasinglulu 13*91f16700SchasingluluCORE_TYPE := a72 14*91f16700Schasinglulu 15*91f16700SchasingluluCACHE_LINE := 6 16*91f16700Schasinglulu 17*91f16700Schasinglulu# set to GIC400 or GIC500 18*91f16700SchasingluluGIC := GIC400 19*91f16700Schasinglulu 20*91f16700Schasinglulu# set to CCI400 or CCN504 or CCN508 21*91f16700SchasingluluINTERCONNECT := CCI400 22*91f16700Schasinglulu 23*91f16700Schasinglulu# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 24*91f16700SchasingluluCHASSIS := 2 25*91f16700Schasinglulu 26*91f16700Schasinglulu# TZC IP Details TZC used is TZC380 or TZC400 27*91f16700SchasingluluTZC_ID := TZC400 28*91f16700Schasinglulu 29*91f16700Schasinglulu# CONSOLE Details available is NS16550 or PL011 30*91f16700SchasingluluCONSOLE := NS16550 31*91f16700Schasinglulu 32*91f16700Schasinglulu # Select the DDR PHY generation to be used 33*91f16700SchasingluluPLAT_DDR_PHY := PHY_GEN1 34*91f16700Schasinglulu 35*91f16700SchasingluluPHYS_SYS := 64 36*91f16700Schasinglulu 37*91f16700Schasinglulu# ddr controller - set to MMDC or NXP 38*91f16700SchasingluluDDRCNTLR := NXP 39*91f16700Schasinglulu 40*91f16700Schasinglulu# ddr phy - set to NXP or SNPS 41*91f16700SchasingluluDDRPHY := NXP 42*91f16700Schasinglulu 43*91f16700Schasinglulu# Area of OCRAM reserved by ROM code 44*91f16700SchasingluluNXP_ROM_RSVD := 0x8000 45*91f16700Schasinglulu 46*91f16700Schasinglulu# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 47*91f16700Schasinglulu# Input to CST create_hdr_esbc tool 48*91f16700SchasingluluCSF_HDR_SZ := 0x4000 49*91f16700Schasinglulu 50*91f16700Schasinglulu# In IMAGE_BL2, compile time flag for handling Cache coherency 51*91f16700Schasinglulu# with CAAM for BL2 running from OCRAM 52*91f16700SchasingluluSEC_MEM_NON_COHERENT := yes 53*91f16700Schasinglulu 54*91f16700Schasinglulu# OCRAM MAP 55*91f16700SchasingluluOCRAM_START_ADDR := 0x10000000 56*91f16700SchasingluluOCRAM_SIZE := 0x20000 57*91f16700Schasinglulu 58*91f16700Schasinglulu# BL2 binary is placed at start of OCRAM. 59*91f16700Schasinglulu# Also used by create_pbl.mk. 60*91f16700SchasingluluBL2_BASE := 0x10000000 61*91f16700Schasinglulu 62*91f16700Schasinglulu# After BL2 bin, OCRAM is used by ROM Code: 63*91f16700Schasinglulu# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1) 64*91f16700Schasinglulu 65*91f16700Schasinglulu# After ROM Code, OCRAM is used by CSF header. 66*91f16700Schasinglulu# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1) 67*91f16700Schasinglulu 68*91f16700Schasinglulu# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ) 69*91f16700Schasinglulu# This value should be greater than BL2_TEXT_LIMIT 70*91f16700Schasinglulu# Input to CST create_hdr_isbc tool 71*91f16700SchasingluluBL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ)))) 72*91f16700Schasinglulu# Covert to HEX to be used by create_pbl.mk 73*91f16700SchasingluluBL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc) 74*91f16700Schasinglulu 75*91f16700Schasinglulu# Core Errata 76*91f16700SchasingluluERRATA_A72_859971 := 1 77*91f16700Schasinglulu 78*91f16700Schasinglulu# SoC ERRATAS 79*91f16700SchasingluluERRATA_SOC_A008850 := 1 80*91f16700SchasingluluERRATA_SOC_A010539 := 1 81*91f16700Schasinglulu 82*91f16700Schasinglulu# DDR Errata 83*91f16700SchasingluluERRATA_DDR_A008511 := 1 84*91f16700SchasingluluERRATA_DDR_A009803 := 1 85*91f16700SchasingluluERRATA_DDR_A009942 := 1 86*91f16700SchasingluluERRATA_DDR_A010165 := 1 87*91f16700Schasinglulu 88*91f16700Schasinglulu# enable dynamic memory mapping 89*91f16700SchasingluluPLAT_XLAT_TABLES_DYNAMIC := 1 90*91f16700Schasinglulu 91*91f16700Schasinglulu# Define Endianness of each module 92*91f16700SchasingluluNXP_GUR_ENDIANNESS := BE 93*91f16700SchasingluluNXP_DDR_ENDIANNESS := BE 94*91f16700SchasingluluNXP_SEC_ENDIANNESS := BE 95*91f16700SchasingluluNXP_SFP_ENDIANNESS := BE 96*91f16700SchasingluluNXP_SNVS_ENDIANNESS := BE 97*91f16700SchasingluluNXP_ESDHC_ENDIANNESS := BE 98*91f16700SchasingluluNXP_QSPI_ENDIANNESS := BE 99*91f16700SchasingluluNXP_FSPI_ENDIANNESS := BE 100*91f16700SchasingluluNXP_SCFG_ENDIANNESS := BE 101*91f16700SchasingluluNXP_GPIO_ENDIANNESS := BE 102*91f16700SchasingluluNXP_IFC_ENDIANNESS := BE 103*91f16700Schasinglulu 104*91f16700SchasingluluNXP_SFP_VER := 3_2 105*91f16700Schasinglulu 106*91f16700Schasinglulu# OCRAM ECC Enabled 107*91f16700SchasingluluOCRAM_ECC_EN := yes 108