1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2018-2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <errno.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <common/debug.h> 11*91f16700Schasinglulu #include <ddr.h> 12*91f16700Schasinglulu #include <lib/utils.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <errata.h> 15*91f16700Schasinglulu #include "platform_def.h" 16*91f16700Schasinglulu 17*91f16700Schasinglulu static const struct rc_timing rce[] = { 18*91f16700Schasinglulu {U(1600), U(8), U(7)}, 19*91f16700Schasinglulu {U(1867), U(8), U(7)}, 20*91f16700Schasinglulu {U(2134), U(8), U(9)}, 21*91f16700Schasinglulu {} 22*91f16700Schasinglulu }; 23*91f16700Schasinglulu 24*91f16700Schasinglulu static const struct board_timing udimm[] = { 25*91f16700Schasinglulu {U(0x04), rce, U(0x01020304), U(0x06070805)}, 26*91f16700Schasinglulu }; 27*91f16700Schasinglulu 28*91f16700Schasinglulu int ddr_board_options(struct ddr_info *priv) 29*91f16700Schasinglulu { 30*91f16700Schasinglulu int ret; 31*91f16700Schasinglulu struct memctl_opt *popts = &priv->opt; 32*91f16700Schasinglulu 33*91f16700Schasinglulu if (popts->rdimm) { 34*91f16700Schasinglulu debug("RDIMM parameters not set.\n"); 35*91f16700Schasinglulu return -EINVAL; 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm)); 39*91f16700Schasinglulu if (ret != 0) { 40*91f16700Schasinglulu return ret; 41*91f16700Schasinglulu } 42*91f16700Schasinglulu 43*91f16700Schasinglulu popts->wrlvl_override = U(1); 44*91f16700Schasinglulu popts->wrlvl_sample = U(0x0); /* 32 clocks */ 45*91f16700Schasinglulu popts->ddr_cdr1 = DDR_CDR1_DHC_EN | 46*91f16700Schasinglulu DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); 47*91f16700Schasinglulu popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | 48*91f16700Schasinglulu DDR_CDR2_VREF_TRAIN_EN | 49*91f16700Schasinglulu DDR_CDR2_VREF_RANGE_2; 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* optimize cpo for erratum A-009942 */ 52*91f16700Schasinglulu popts->cpo_sample = U(0x70); 53*91f16700Schasinglulu 54*91f16700Schasinglulu return 0; 55*91f16700Schasinglulu } 56*91f16700Schasinglulu 57*91f16700Schasinglulu long long init_ddr(void) 58*91f16700Schasinglulu { 59*91f16700Schasinglulu int spd_addr[] = { NXP_SPD_EEPROM0 }; 60*91f16700Schasinglulu struct ddr_info info; 61*91f16700Schasinglulu struct sysinfo sys; 62*91f16700Schasinglulu long long dram_size; 63*91f16700Schasinglulu 64*91f16700Schasinglulu zeromem(&sys, sizeof(sys)); 65*91f16700Schasinglulu if (get_clocks(&sys)) { 66*91f16700Schasinglulu ERROR("System clocks are not set\n"); 67*91f16700Schasinglulu assert(0); 68*91f16700Schasinglulu } 69*91f16700Schasinglulu debug("platform clock %lu\n", sys.freq_platform); 70*91f16700Schasinglulu debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); 71*91f16700Schasinglulu debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); 72*91f16700Schasinglulu 73*91f16700Schasinglulu zeromem(&info, sizeof(struct ddr_info)); 74*91f16700Schasinglulu info.num_ctlrs = 1; 75*91f16700Schasinglulu info.dimm_on_ctlr = 1; 76*91f16700Schasinglulu info.clk = get_ddr_freq(&sys, 0); 77*91f16700Schasinglulu info.spd_addr = spd_addr; 78*91f16700Schasinglulu info.ddr[0] = (void *)NXP_DDR_ADDR; 79*91f16700Schasinglulu 80*91f16700Schasinglulu dram_size = dram_init(&info); 81*91f16700Schasinglulu 82*91f16700Schasinglulu if (dram_size < 0) { 83*91f16700Schasinglulu ERROR("DDR init failed.\n"); 84*91f16700Schasinglulu } 85*91f16700Schasinglulu 86*91f16700Schasinglulu #ifdef ERRATA_SOC_A008850 87*91f16700Schasinglulu erratum_a008850_post(); 88*91f16700Schasinglulu #endif 89*91f16700Schasinglulu 90*91f16700Schasinglulu return dram_size; 91*91f16700Schasinglulu } 92