1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright 2018-2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu#include <arch.h> 9*91f16700Schasinglulu#include <asm_macros.S> 10*91f16700Schasinglulu 11*91f16700Schasinglulu#include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 14*91f16700Schasinglulu .globl plat_is_my_cpu_primary 15*91f16700Schasinglulu .globl plat_reset_handler 16*91f16700Schasinglulu .globl platform_mem_init 17*91f16700Schasinglulu 18*91f16700Schasinglulufunc platform_mem1_init 19*91f16700Schasinglulu ret 20*91f16700Schasingluluendfunc platform_mem1_init 21*91f16700Schasinglulu 22*91f16700Schasinglulufunc platform_mem_init 23*91f16700Schasinglulu ret 24*91f16700Schasingluluendfunc platform_mem_init 25*91f16700Schasinglulu 26*91f16700Schasinglulufunc l2_mem_init 27*91f16700Schasinglulu /* Initialize the L2 RAM latency */ 28*91f16700Schasinglulu mrs x1, S3_1_c11_c0_2 29*91f16700Schasinglulu mov x0, #0x1C7 30*91f16700Schasinglulu /* Clear L2 Tag RAM latency and L2 Data RAM latency */ 31*91f16700Schasinglulu bic x1, x1, x0 32*91f16700Schasinglulu /* Set L2 data ram latency bits [2:0] */ 33*91f16700Schasinglulu orr x1, x1, #0x2 34*91f16700Schasinglulu /* set L2 tag ram latency bits [8:6] */ 35*91f16700Schasinglulu orr x1, x1, #0x80 36*91f16700Schasinglulu msr S3_1_c11_c0_2, x1 37*91f16700Schasinglulu isb 38*91f16700Schasinglulu ret 39*91f16700Schasingluluendfunc l2_mem_init 40*91f16700Schasinglulu 41*91f16700Schasinglulufunc apply_platform_errata 42*91f16700Schasinglulu ret 43*91f16700Schasingluluendfunc apply_platform_errata 44*91f16700Schasinglulu 45*91f16700Schasinglulufunc plat_reset_handler 46*91f16700Schasinglulu mov x29, x30 47*91f16700Schasinglulu#if (defined(IMAGE_BL2) && RESET_TO_BL2) 48*91f16700Schasinglulu bl l2_mem_init 49*91f16700Schasinglulu#endif 50*91f16700Schasinglulu bl apply_platform_errata 51*91f16700Schasinglulu 52*91f16700Schasinglulu#if defined(IMAGE_BL31) 53*91f16700Schasinglulu ldr x0, =POLICY_SMMU_PAGESZ_64K 54*91f16700Schasinglulu cbz x0, 1f 55*91f16700Schasinglulu /* Set the SMMU page size in the SACR register */ 56*91f16700Schasinglulu bl _set_smmu_pagesz_64 57*91f16700Schasinglulu#endif 58*91f16700Schasinglulu1: 59*91f16700Schasinglulu /* 60*91f16700Schasinglulu * May be cntfrq_el0 needs to be assigned 61*91f16700Schasinglulu * the value COUNTER_FREQUENCY 62*91f16700Schasinglulu */ 63*91f16700Schasinglulu mov x30, x29 64*91f16700Schasinglulu ret 65*91f16700Schasingluluendfunc plat_reset_handler 66*91f16700Schasinglulu 67*91f16700Schasinglulu/* 68*91f16700Schasinglulu * void plat_secondary_cold_boot_setup (void); 69*91f16700Schasinglulu * 70*91f16700Schasinglulu * This function performs any platform specific actions 71*91f16700Schasinglulu * needed for a secondary cpu after a cold reset e.g 72*91f16700Schasinglulu * mark the cpu's presence, mechanism to place it in a 73*91f16700Schasinglulu * holding pen etc. 74*91f16700Schasinglulu */ 75*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 76*91f16700Schasinglulu /* ls1046a does not do cold boot for secondary CPU */ 77*91f16700Schasinglulucb_panic: 78*91f16700Schasinglulu b cb_panic 79*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 80*91f16700Schasinglulu 81*91f16700Schasinglulu/* 82*91f16700Schasinglulu * unsigned int plat_is_my_cpu_primary (void); 83*91f16700Schasinglulu * 84*91f16700Schasinglulu * Find out whether the current cpu is the primary cpu. 85*91f16700Schasinglulu */ 86*91f16700Schasinglulufunc plat_is_my_cpu_primary 87*91f16700Schasinglulu mrs x0, mpidr_el1 88*91f16700Schasinglulu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 89*91f16700Schasinglulu cmp x0, 0x0 90*91f16700Schasinglulu cset w0, eq 91*91f16700Schasinglulu ret 92*91f16700Schasingluluendfunc plat_is_my_cpu_primary 93