1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright 2018-2021 NXP 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu# 7*91f16700Schasinglulu#------------------------------------------------------------------------------ 8*91f16700Schasinglulu# 9*91f16700Schasinglulu# This file contains the basic architecture definitions that drive the build 10*91f16700Schasinglulu# 11*91f16700Schasinglulu# ----------------------------------------------------------------------------- 12*91f16700Schasinglulu 13*91f16700SchasingluluCORE_TYPE := a72 14*91f16700Schasinglulu 15*91f16700SchasingluluCACHE_LINE := 6 16*91f16700Schasinglulu 17*91f16700Schasinglulu# Set to GIC400 or GIC500 18*91f16700SchasingluluGIC := GIC500 19*91f16700Schasinglulu 20*91f16700Schasinglulu# Set to CCI400 or CCN504 or CCN508 21*91f16700SchasingluluINTERCONNECT := CCI400 22*91f16700Schasinglulu 23*91f16700Schasinglulu# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 24*91f16700SchasingluluCHASSIS := 3_2 25*91f16700Schasinglulu 26*91f16700Schasinglulu# TZC used is TZC380 or TZC400 27*91f16700SchasingluluTZC_ID := TZC400 28*91f16700Schasinglulu 29*91f16700Schasinglulu# CONSOLE is NS16550 or PL011 30*91f16700SchasingluluCONSOLE := NS16550 31*91f16700Schasinglulu 32*91f16700Schasinglulu# DDR PHY generation to be used 33*91f16700SchasingluluPLAT_DDR_PHY := PHY_GEN1 34*91f16700Schasinglulu 35*91f16700SchasingluluPHYS_SYS := 64 36*91f16700Schasinglulu 37*91f16700Schasinglulu# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 38*91f16700Schasinglulu# Input to CST create_hdr_esbc tool 39*91f16700SchasingluluCSF_HDR_SZ := 0x3000 40*91f16700Schasinglulu 41*91f16700Schasinglulu# In IMAGE_BL2, compile time flag for handling Cache coherency 42*91f16700Schasinglulu# with CAAM for BL2 running from OCRAM 43*91f16700SchasingluluSEC_MEM_NON_COHERENT := yes 44*91f16700Schasinglulu 45*91f16700Schasinglulu# OCRAM MAP for BL2 46*91f16700Schasinglulu# Before BL2 47*91f16700Schasinglulu# 0x18000000 - 0x18009fff -> Used by ROM code 48*91f16700Schasinglulu# 0x1800a000 - 0x1800dfff -> CSF header for BL2 49*91f16700Schasinglulu# For FlexSFlexSPI boot 50*91f16700Schasinglulu# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary 51*91f16700Schasinglulu# For SD boot 52*91f16700Schasinglulu# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary 53*91f16700Schasinglulu# 0x18030000 - 0x18040000 -> Reserved for SD buffer 54*91f16700SchasingluluOCRAM_START_ADDR := 0x18000000 55*91f16700SchasingluluOCRAM_SIZE := 0x40000 56*91f16700Schasinglulu 57*91f16700Schasinglulu# Area of OCRAM reserved by ROM code 58*91f16700SchasingluluNXP_ROM_RSVD := 0xa000 59*91f16700Schasinglulu 60*91f16700Schasinglulu# Location of BL2 on OCRAM 61*91f16700SchasingluluBL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) 62*91f16700Schasinglulu 63*91f16700Schasinglulu# Covert to HEX to be used by create_pbl.mk 64*91f16700SchasingluluBL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) 65*91f16700Schasinglulu 66*91f16700Schasinglulu# BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD) 67*91f16700Schasinglulu# This value BL2_HDR_LOC + CSF_HDR_SZ should not 68*91f16700Schasinglulu# overalp with BL2_BASE 69*91f16700Schasinglulu# Input to CST create_hdr_isbc tool 70*91f16700SchasingluluBL2_HDR_LOC := 0x1800A000 71*91f16700Schasinglulu 72*91f16700Schasinglulu# SoC ERRATAS to be enabled 73*91f16700Schasinglulu 74*91f16700Schasinglulu# DDR ERRATA 75*91f16700SchasingluluERRATA_DDR_A009803 := 1 76*91f16700SchasingluluERRATA_DDR_A009942 := 1 77*91f16700SchasingluluERRATA_DDR_A010165 := 1 78*91f16700Schasinglulu 79*91f16700Schasinglulu# Enable dynamic memory mapping 80*91f16700SchasingluluPLAT_XLAT_TABLES_DYNAMIC := 1 81*91f16700Schasinglulu 82*91f16700Schasinglulu# Define Endianness of each module 83*91f16700SchasingluluNXP_GUR_ENDIANNESS := LE 84*91f16700SchasingluluNXP_DDR_ENDIANNESS := LE 85*91f16700SchasingluluNXP_SEC_ENDIANNESS := LE 86*91f16700SchasingluluNXP_SFP_ENDIANNESS := LE 87*91f16700SchasingluluNXP_SNVS_ENDIANNESS := LE 88*91f16700SchasingluluNXP_ESDHC_ENDIANNESS := LE 89*91f16700SchasingluluNXP_QSPI_ENDIANNESS := LE 90*91f16700SchasingluluNXP_FSPI_ENDIANNESS := LE 91*91f16700SchasingluluNXP_SCFG_ENDIANNESS := LE 92*91f16700SchasingluluNXP_GPIO_ENDIANNESS := LE 93*91f16700Schasinglulu 94*91f16700SchasingluluNXP_SFP_VER := 3_4 95*91f16700Schasinglulu 96*91f16700Schasinglulu# OCRAM ECC Enabled 97*91f16700SchasingluluOCRAM_ECC_EN := yes 98