1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2018-2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_DEF_H 8*91f16700Schasinglulu #define PLAT_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <cortex_a72.h> 12*91f16700Schasinglulu /* 13*91f16700Schasinglulu * Required without TBBR. 14*91f16700Schasinglulu * To include the defines for DDR PHY 15*91f16700Schasinglulu * Images. 16*91f16700Schasinglulu */ 17*91f16700Schasinglulu #include <tbbr_img_def.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu #include <policy.h> 20*91f16700Schasinglulu #include <soc.h> 21*91f16700Schasinglulu 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define NXP_SYSCLK_FREQ 100000000 24*91f16700Schasinglulu #define NXP_DDRCLK_FREQ 100000000 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* UART related definition */ 27*91f16700Schasinglulu #define NXP_CONSOLE_ADDR NXP_UART_ADDR 28*91f16700Schasinglulu #define NXP_CONSOLE_BAUDRATE 115200 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define NXP_SPD_EEPROM0 0x51 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* Size of cacheable stacks */ 33*91f16700Schasinglulu #if defined(IMAGE_BL2) 34*91f16700Schasinglulu #if defined(TRUSTED_BOARD_BOOT) 35*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x2000 36*91f16700Schasinglulu #else 37*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x1000 38*91f16700Schasinglulu #endif 39*91f16700Schasinglulu #elif defined(IMAGE_BL31) 40*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x1000 41*91f16700Schasinglulu #endif 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* SD block buffer */ 44*91f16700Schasinglulu #define NXP_SD_BLOCK_BUF_SIZE (0xC000) 45*91f16700Schasinglulu 46*91f16700Schasinglulu #ifdef SD_BOOT 47*91f16700Schasinglulu #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 48*91f16700Schasinglulu - NXP_SD_BLOCK_BUF_SIZE) 49*91f16700Schasinglulu #else 50*91f16700Schasinglulu #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 51*91f16700Schasinglulu #endif 52*91f16700Schasinglulu #define BL2_TEXT_LIMIT (BL2_LIMIT) 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* IO defines as needed by IO driver framework */ 55*91f16700Schasinglulu #define MAX_IO_DEVICES 4 56*91f16700Schasinglulu #define MAX_IO_BLOCK_DEVICES 1 57*91f16700Schasinglulu #define MAX_IO_HANDLES 4 58*91f16700Schasinglulu 59*91f16700Schasinglulu #define BL31_WDOG_SEC 89 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* 62*91f16700Schasinglulu * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 63*91f16700Schasinglulu * terminology. On a GICv2 system or mode, the lists will be merged and treated 64*91f16700Schasinglulu * as Group 0 interrupts. 65*91f16700Schasinglulu */ 66*91f16700Schasinglulu #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 67*91f16700Schasinglulu INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 68*91f16700Schasinglulu GIC_INTR_CFG_EDGE) 69*91f16700Schasinglulu 70*91f16700Schasinglulu /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 71*91f16700Schasinglulu #define PLAT_LS_G0_IRQ_PROPS(grp) \ 72*91f16700Schasinglulu INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 73*91f16700Schasinglulu GIC_INTR_CFG_EDGE), \ 74*91f16700Schasinglulu INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ 75*91f16700Schasinglulu GIC_INTR_CFG_LEVEL) 76*91f16700Schasinglulu #endif /* PLAT_DEF_H */ 77