1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <mmio.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <plat_common.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu void erratum_a010539(void) 13*91f16700Schasinglulu { 14*91f16700Schasinglulu if (get_boot_dev() == BOOT_DEVICE_QSPI) { 15*91f16700Schasinglulu unsigned int *porsr1 = (void *)(NXP_DCFG_ADDR + 16*91f16700Schasinglulu DCFG_PORSR1_OFFSET); 17*91f16700Schasinglulu uint32_t val; 18*91f16700Schasinglulu 19*91f16700Schasinglulu val = (gur_in32(porsr1) & ~PORSR1_RCW_MASK); 20*91f16700Schasinglulu mmio_write_32((uint32_t)(NXP_DCSR_DCFG_ADDR + 21*91f16700Schasinglulu DCFG_DCSR_PORCR1_OFFSET), htobe32(val)); 22*91f16700Schasinglulu /* Erratum need to set '1' to all bits for reserved SCFG register 0x1a8 */ 23*91f16700Schasinglulu mmio_write_32((uint32_t)(NXP_SCFG_ADDR + 0x1a8), 24*91f16700Schasinglulu htobe32(0xffffffff)); 25*91f16700Schasinglulu } 26*91f16700Schasinglulu } 27