1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu #include <cci.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <ls_interconnect.h> 10*91f16700Schasinglulu #include <mmio.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu void erratum_a008850_early(void) 15*91f16700Schasinglulu { 16*91f16700Schasinglulu /* part 1 of 2 */ 17*91f16700Schasinglulu uintptr_t cci_base = NXP_CCI_ADDR; 18*91f16700Schasinglulu uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* enabling forced barrier termination on CCI400 */ 21*91f16700Schasinglulu mmio_write_32(cci_base + CTRL_OVERRIDE_REG, 22*91f16700Schasinglulu (val | CCI_TERMINATE_BARRIER_TX)); 23*91f16700Schasinglulu 24*91f16700Schasinglulu } 25*91f16700Schasinglulu 26*91f16700Schasinglulu void erratum_a008850_post(void) 27*91f16700Schasinglulu { 28*91f16700Schasinglulu /* part 2 of 2 */ 29*91f16700Schasinglulu uintptr_t cci_base = NXP_CCI_ADDR; 30*91f16700Schasinglulu uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* Clear the BARRIER_TX bit */ 33*91f16700Schasinglulu val = val & ~(CCI_TERMINATE_BARRIER_TX); 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* 36*91f16700Schasinglulu * Disable barrier termination on CCI400, allowing 37*91f16700Schasinglulu * barriers to propagate across CCI 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val); 40*91f16700Schasinglulu 41*91f16700Schasinglulu INFO("SoC workaround for Errata A008850 Post-Phase was applied\n"); 42*91f16700Schasinglulu } 43