1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2018-2020 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef BL31_DATA_H 9*91f16700Schasinglulu #define BL31_DATA_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define SECURE_DATA_BASE NXP_OCRAM_ADDR 12*91f16700Schasinglulu #define SECURE_DATA_SIZE NXP_OCRAM_SIZE 13*91f16700Schasinglulu #define SECURE_DATA_TOP (SECURE_DATA_BASE + SECURE_DATA_SIZE) 14*91f16700Schasinglulu #define SMC_REGION_SIZE 0x80 15*91f16700Schasinglulu #define SMC_GLBL_BASE (SECURE_DATA_TOP - SMC_REGION_SIZE) 16*91f16700Schasinglulu #define BC_PSCI_DATA_SIZE 0xC0 17*91f16700Schasinglulu #define BC_PSCI_BASE (SMC_GLBL_BASE - BC_PSCI_DATA_SIZE) 18*91f16700Schasinglulu #define SECONDARY_TOP BC_PSCI_BASE 19*91f16700Schasinglulu 20*91f16700Schasinglulu #define SEC_PSCI_DATA_SIZE 0xC0 21*91f16700Schasinglulu #define SEC_REGION_SIZE SEC_PSCI_DATA_SIZE 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* SMC global data */ 24*91f16700Schasinglulu #define BOOTLOC_OFFSET 0x0 25*91f16700Schasinglulu #define BOOT_SVCS_OSET 0x8 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* offset to prefetch disable mask */ 28*91f16700Schasinglulu #define PREFETCH_DIS_OFFSET 0x10 29*91f16700Schasinglulu /* must reference last smc global entry */ 30*91f16700Schasinglulu #define LAST_SMC_GLBL_OFFSET 0x18 31*91f16700Schasinglulu 32*91f16700Schasinglulu #define SMC_TASK_OFFSET 0xC 33*91f16700Schasinglulu #define TSK_START_OFFSET 0x0 34*91f16700Schasinglulu #define TSK_DONE_OFFSET 0x4 35*91f16700Schasinglulu #define TSK_CORE_OFFSET 0x8 36*91f16700Schasinglulu #define SMC_TASK1_BASE (SMC_GLBL_BASE + 32) 37*91f16700Schasinglulu #define SMC_TASK2_BASE (SMC_TASK1_BASE + SMC_TASK_OFFSET) 38*91f16700Schasinglulu #define SMC_TASK3_BASE (SMC_TASK2_BASE + SMC_TASK_OFFSET) 39*91f16700Schasinglulu #define SMC_TASK4_BASE (SMC_TASK3_BASE + SMC_TASK_OFFSET) 40*91f16700Schasinglulu 41*91f16700Schasinglulu /* psci data area offsets */ 42*91f16700Schasinglulu #define CORE_STATE_DATA 0x0 43*91f16700Schasinglulu #define SPSR_EL3_DATA 0x8 44*91f16700Schasinglulu #define CNTXT_ID_DATA 0x10 45*91f16700Schasinglulu #define START_ADDR_DATA 0x18 46*91f16700Schasinglulu #define LINK_REG_DATA 0x20 47*91f16700Schasinglulu #define GICC_CTLR_DATA 0x28 48*91f16700Schasinglulu #define ABORT_FLAG_DATA 0x30 49*91f16700Schasinglulu #define SCTLR_DATA 0x38 50*91f16700Schasinglulu #define CPUECTLR_DATA 0x40 51*91f16700Schasinglulu #define AUX_01_DATA 0x48 /* usage defined per SoC */ 52*91f16700Schasinglulu #define AUX_02_DATA 0x50 /* usage defined per SoC */ 53*91f16700Schasinglulu #define AUX_03_DATA 0x58 /* usage defined per SoC */ 54*91f16700Schasinglulu #define AUX_04_DATA 0x60 /* usage defined per SoC */ 55*91f16700Schasinglulu #define AUX_05_DATA 0x68 /* usage defined per SoC */ 56*91f16700Schasinglulu #define AUX_06_DATA 0x70 /* usage defined per SoC */ 57*91f16700Schasinglulu #define AUX_07_DATA 0x78 /* usage defined per SoC */ 58*91f16700Schasinglulu #define SCR_EL3_DATA 0x80 59*91f16700Schasinglulu #define HCR_EL2_DATA 0x88 60*91f16700Schasinglulu 61*91f16700Schasinglulu #endif /* BL31_DATA_H */ 62