1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu 9*91f16700Schasinglulu#include <soc_default_base_addr.h> 10*91f16700Schasinglulu#include <soc_default_helper_macros.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu.global ocram_init 13*91f16700Schasinglulu 14*91f16700Schasinglulu/* 15*91f16700Schasinglulu * void ocram_init(uintptr_t start_addr, size_t size) 16*91f16700Schasinglulu * 17*91f16700Schasinglulu * This function will do OCRAM ECC. 18*91f16700Schasinglulu * OCRAM is initialized with 64-bit writes and then a write 19*91f16700Schasinglulu * performed to address 0x0010_0534 with the value 0x0000_0008. 20*91f16700Schasinglulu * 21*91f16700Schasinglulu * x0: start_addr 22*91f16700Schasinglulu * x1: size in bytes 23*91f16700Schasinglulu * Called from C 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu 26*91f16700Schasinglulufunc ocram_init 27*91f16700Schasinglulu /* save the aarch32/64 non-volatile registers */ 28*91f16700Schasinglulu stp x4, x5, [sp, #-16]! 29*91f16700Schasinglulu stp x6, x7, [sp, #-16]! 30*91f16700Schasinglulu stp x8, x9, [sp, #-16]! 31*91f16700Schasinglulu stp x10, x11, [sp, #-16]! 32*91f16700Schasinglulu stp x12, x13, [sp, #-16]! 33*91f16700Schasinglulu stp x18, x30, [sp, #-16]! 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* convert bytes to 64-byte chunks */ 36*91f16700Schasinglulu lsr x1, x1, #6 37*91f16700Schasinglulu1: 38*91f16700Schasinglulu /* for each location, read and write-back */ 39*91f16700Schasinglulu dc ivac, x0 40*91f16700Schasinglulu dsb sy 41*91f16700Schasinglulu ldp x4, x5, [x0] 42*91f16700Schasinglulu ldp x6, x7, [x0, #16] 43*91f16700Schasinglulu ldp x8, x9, [x0, #32] 44*91f16700Schasinglulu ldp x10, x11, [x0, #48] 45*91f16700Schasinglulu stp x4, x5, [x0] 46*91f16700Schasinglulu stp x6, x7, [x0, #16] 47*91f16700Schasinglulu stp x8, x9, [x0, #32] 48*91f16700Schasinglulu stp x10, x11, [x0, #48] 49*91f16700Schasinglulu dc cvac, x0 50*91f16700Schasinglulu 51*91f16700Schasinglulu sub x1, x1, #1 52*91f16700Schasinglulu cbz x1, 2f 53*91f16700Schasinglulu add x0, x0, #64 54*91f16700Schasinglulu b 1b 55*91f16700Schasinglulu2: 56*91f16700Schasinglulu /* Clear OCRAM ECC status bit in SBEESR2 and MBEESR2 */ 57*91f16700Schasinglulu ldr w1, =OCRAM_EESR_MASK 58*91f16700Schasinglulu ldr x0, =DCFG_SBEESR2_ADDR 59*91f16700Schasinglulu str w1, [x0] 60*91f16700Schasinglulu ldr x0, =DCFG_MBEESR2_ADDR 61*91f16700Schasinglulu str w1, [x0] 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* restore the aarch32/64 non-volatile registers */ 64*91f16700Schasinglulu ldp x18, x30, [sp], #16 65*91f16700Schasinglulu ldp x12, x13, [sp], #16 66*91f16700Schasinglulu ldp x10, x11, [sp], #16 67*91f16700Schasinglulu ldp x8, x9, [sp], #16 68*91f16700Schasinglulu ldp x6, x7, [sp], #16 69*91f16700Schasinglulu ldp x4, x5, [sp], #16 70*91f16700Schasinglulu ret 71*91f16700Schasingluluendfunc ocram_init 72