1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2021 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <assert.h> 9*91f16700Schasinglulu #include <errno.h> 10*91f16700Schasinglulu #include <stddef.h> 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu #include <stdio.h> 13*91f16700Schasinglulu #include <stdlib.h> 14*91f16700Schasinglulu #include <string.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #include <platform_def.h> 17*91f16700Schasinglulu #include <common/debug.h> 18*91f16700Schasinglulu #ifndef NXP_COINED_BB 19*91f16700Schasinglulu #include <flash_info.h> 20*91f16700Schasinglulu #include <fspi.h> 21*91f16700Schasinglulu #include <fspi_api.h> 22*91f16700Schasinglulu #endif 23*91f16700Schasinglulu #include <lib/mmio.h> 24*91f16700Schasinglulu #ifdef NXP_COINED_BB 25*91f16700Schasinglulu #include <snvs.h> 26*91f16700Schasinglulu #else 27*91f16700Schasinglulu #include <xspi_error_codes.h> 28*91f16700Schasinglulu #endif 29*91f16700Schasinglulu 30*91f16700Schasinglulu #include <plat_nv_storage.h> 31*91f16700Schasinglulu 32*91f16700Schasinglulu /*This structure will be a static structure and 33*91f16700Schasinglulu * will be populated as first step of BL2 booting-up. 34*91f16700Schasinglulu * fspi_strorage.c . To be located in the fspi driver folder. 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu 37*91f16700Schasinglulu static nv_app_data_t nv_app_data; 38*91f16700Schasinglulu 39*91f16700Schasinglulu int read_nv_app_data(void) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu int ret = 0; 42*91f16700Schasinglulu 43*91f16700Schasinglulu #ifdef NXP_COINED_BB 44*91f16700Schasinglulu uint8_t *nv_app_data_array = (uint8_t *) &nv_app_data; 45*91f16700Schasinglulu uint8_t offset = 0U; 46*91f16700Schasinglulu 47*91f16700Schasinglulu ret = snvs_read_app_data(); 48*91f16700Schasinglulu do { 49*91f16700Schasinglulu nv_app_data_array[offset] = snvs_read_app_data_bit(offset); 50*91f16700Schasinglulu offset++; 51*91f16700Schasinglulu 52*91f16700Schasinglulu } while (offset < APP_DATA_MAX_OFFSET); 53*91f16700Schasinglulu snvs_clear_app_data(); 54*91f16700Schasinglulu #else 55*91f16700Schasinglulu uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR; 56*91f16700Schasinglulu 57*91f16700Schasinglulu ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR); 58*91f16700Schasinglulu 59*91f16700Schasinglulu if (ret != XSPI_SUCCESS) { 60*91f16700Schasinglulu ERROR("Failed to initialized driver flexspi-nor.\n"); 61*91f16700Schasinglulu ERROR("exiting warm-reset request.\n"); 62*91f16700Schasinglulu return -ENODEV; 63*91f16700Schasinglulu } 64*91f16700Schasinglulu 65*91f16700Schasinglulu xspi_read(nv_base_addr, 66*91f16700Schasinglulu (uint32_t *)&nv_app_data, sizeof(nv_app_data_t)); 67*91f16700Schasinglulu xspi_sector_erase((uint32_t) nv_base_addr, 68*91f16700Schasinglulu F_SECTOR_ERASE_SZ); 69*91f16700Schasinglulu #endif 70*91f16700Schasinglulu return ret; 71*91f16700Schasinglulu } 72*91f16700Schasinglulu 73*91f16700Schasinglulu int wr_nv_app_data(int data_offset, 74*91f16700Schasinglulu uint8_t *data, 75*91f16700Schasinglulu int data_size) 76*91f16700Schasinglulu { 77*91f16700Schasinglulu int ret = 0; 78*91f16700Schasinglulu #ifdef NXP_COINED_BB 79*91f16700Schasinglulu #if !TRUSTED_BOARD_BOOT 80*91f16700Schasinglulu snvs_disable_zeroize_lp_gpr(); 81*91f16700Schasinglulu #endif 82*91f16700Schasinglulu /* In case LP SecMon General purpose register, 83*91f16700Schasinglulu * only 1 bit flags can be saved. 84*91f16700Schasinglulu */ 85*91f16700Schasinglulu if ((data_size > 1) || (*data != DEFAULT_SET_VALUE)) { 86*91f16700Schasinglulu ERROR("Only binary value is allowed to be written.\n"); 87*91f16700Schasinglulu ERROR("Use flash instead of SNVS GPR as NV location.\n"); 88*91f16700Schasinglulu return -ENODEV; 89*91f16700Schasinglulu } 90*91f16700Schasinglulu snvs_write_app_data_bit(data_offset); 91*91f16700Schasinglulu #else 92*91f16700Schasinglulu uint8_t read_val[sizeof(nv_app_data_t)]; 93*91f16700Schasinglulu uint8_t ready_to_write_val[sizeof(nv_app_data_t)]; 94*91f16700Schasinglulu uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR; 95*91f16700Schasinglulu 96*91f16700Schasinglulu assert((nv_base_addr + data_offset + data_size) <= (nv_base_addr + F_SECTOR_ERASE_SZ)); 97*91f16700Schasinglulu 98*91f16700Schasinglulu ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR); 99*91f16700Schasinglulu 100*91f16700Schasinglulu if (ret != XSPI_SUCCESS) { 101*91f16700Schasinglulu ERROR("Failed to initialized driver flexspi-nor.\n"); 102*91f16700Schasinglulu ERROR("exiting warm-reset request.\n"); 103*91f16700Schasinglulu return -ENODEV; 104*91f16700Schasinglulu } 105*91f16700Schasinglulu 106*91f16700Schasinglulu ret = xspi_read(nv_base_addr + data_offset, (uint32_t *)read_val, data_size); 107*91f16700Schasinglulu 108*91f16700Schasinglulu memset(ready_to_write_val, READY_TO_WRITE_VALUE, ARRAY_SIZE(ready_to_write_val)); 109*91f16700Schasinglulu 110*91f16700Schasinglulu if (memcmp(read_val, ready_to_write_val, data_size) == 0) { 111*91f16700Schasinglulu xspi_write(nv_base_addr + data_offset, data, data_size); 112*91f16700Schasinglulu } 113*91f16700Schasinglulu #endif 114*91f16700Schasinglulu 115*91f16700Schasinglulu return ret; 116*91f16700Schasinglulu } 117*91f16700Schasinglulu 118*91f16700Schasinglulu const nv_app_data_t *get_nv_data(void) 119*91f16700Schasinglulu { 120*91f16700Schasinglulu return (const nv_app_data_t *) &nv_app_data; 121*91f16700Schasinglulu } 122