1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright 2020 NXP 3*91f16700Schasinglulu# Copyright (c) 2023, Arm Limited. All rights reserved. 4*91f16700Schasinglulu# 5*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu# 7*91f16700Schasinglulu#----------------------------------------------------------------------------- 8*91f16700Schasingluluifeq (${DDR_FIP_IO_STORAGE_ADDED},) 9*91f16700Schasinglulu 10*91f16700Schasinglulu$(eval $(call add_define, PLAT_DEF_FIP_UUID)) 11*91f16700Schasinglulu$(eval $(call add_define, PLAT_TBBR_IMG_DEF)) 12*91f16700Schasinglulu$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2)) 13*91f16700Schasinglulu 14*91f16700SchasingluluDDR_FIP_IO_STORAGE_ADDED := 1 15*91f16700Schasinglulu$(eval $(call add_define,CONFIG_DDR_FIP_IMAGE)) 16*91f16700Schasinglulu 17*91f16700SchasingluluFIP_HANDLER_PATH := ${PLAT_COMMON_PATH}/fip_handler 18*91f16700SchasingluluFIP_HANDLER_COMMON_PATH := ${FIP_HANDLER_PATH}/common 19*91f16700SchasingluluDDR_FIP_IO_STORAGE_PATH := ${FIP_HANDLER_PATH}/ddr_fip 20*91f16700Schasinglulu 21*91f16700SchasingluluPLAT_INCLUDES += -I${FIP_HANDLER_COMMON_PATH}\ 22*91f16700Schasinglulu -I$(DDR_FIP_IO_STORAGE_PATH) 23*91f16700Schasinglulu 24*91f16700SchasingluluDDR_FIP_IO_SOURCES += $(DDR_FIP_IO_STORAGE_PATH)/ddr_io_storage.c 25*91f16700Schasinglulu 26*91f16700Schasingluluifeq (${BL_COMM_DDR_FIP_IO_NEEDED},yes) 27*91f16700SchasingluluBL_COMMON_SOURCES += ${DDR_FIP_IO_SOURCES} 28*91f16700Schasingluluelse 29*91f16700Schasingluluifeq (${BL2_DDR_FIP_IO_NEEDED},yes) 30*91f16700SchasingluluBL2_SOURCES += ${DDR_FIP_IO_SOURCES} 31*91f16700Schasingluluendif 32*91f16700Schasingluluifeq (${BL31_DDR_FIP_IO_NEEDED},yes) 33*91f16700SchasingluluBL31_SOURCES += ${DDR_FIP_IO_SOURCES} 34*91f16700Schasingluluendif 35*91f16700Schasingluluendif 36*91f16700Schasingluluendif 37*91f16700Schasinglulu#------------------------------------------------ 38