1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu# Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*91f16700Schasinglulu# 5*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu# 7*91f16700Schasinglulu 8*91f16700SchasingluluTZDRAM_BASE := 0xFF800000 9*91f16700Schasinglulu$(eval $(call add_define,TZDRAM_BASE)) 10*91f16700Schasinglulu 11*91f16700SchasingluluERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 12*91f16700Schasinglulu$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) 13*91f16700Schasinglulu 14*91f16700SchasingluluPLATFORM_CLUSTER_COUNT := 2 15*91f16700Schasinglulu$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 16*91f16700Schasinglulu 17*91f16700SchasingluluPLATFORM_MAX_CPUS_PER_CLUSTER := 4 18*91f16700Schasinglulu$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 19*91f16700Schasinglulu 20*91f16700SchasingluluMAX_XLAT_TABLES := 10 21*91f16700Schasinglulu$(eval $(call add_define,MAX_XLAT_TABLES)) 22*91f16700Schasinglulu 23*91f16700SchasingluluMAX_MMAP_REGIONS := 16 24*91f16700Schasinglulu$(eval $(call add_define,MAX_MMAP_REGIONS)) 25*91f16700Schasinglulu 26*91f16700SchasingluluENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1 27*91f16700Schasinglulu 28*91f16700SchasingluluPLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \ 29*91f16700Schasinglulu -I${SOC_DIR}/drivers/se 30*91f16700Schasinglulu 31*91f16700SchasingluluBL31_SOURCES += ${TEGRA_GICv2_SOURCES} \ 32*91f16700Schasinglulu drivers/ti/uart/aarch64/16550_console.S \ 33*91f16700Schasinglulu lib/cpus/aarch64/cortex_a53.S \ 34*91f16700Schasinglulu lib/cpus/aarch64/cortex_a57.S \ 35*91f16700Schasinglulu ${TEGRA_DRIVERS}/bpmp/bpmp.c \ 36*91f16700Schasinglulu ${TEGRA_DRIVERS}/flowctrl/flowctrl.c \ 37*91f16700Schasinglulu ${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \ 38*91f16700Schasinglulu ${TEGRA_DRIVERS}/pmc/pmc.c \ 39*91f16700Schasinglulu ${SOC_DIR}/plat_psci_handlers.c \ 40*91f16700Schasinglulu ${SOC_DIR}/plat_setup.c \ 41*91f16700Schasinglulu ${SOC_DIR}/drivers/se/security_engine.c \ 42*91f16700Schasinglulu ${SOC_DIR}/plat_secondary.c \ 43*91f16700Schasinglulu ${SOC_DIR}/plat_sip_calls.c 44*91f16700Schasinglulu 45*91f16700Schasinglulu# Enable workarounds for selected Cortex-A57 erratas. 46*91f16700SchasingluluA57_DISABLE_NON_TEMPORAL_HINT := 1 47*91f16700SchasingluluERRATA_A57_826974 := 1 48*91f16700SchasingluluERRATA_A57_826977 := 1 49*91f16700SchasingluluERRATA_A57_828024 := 1 50*91f16700SchasingluluERRATA_A57_833471 := 1 51*91f16700Schasinglulu 52*91f16700Schasinglulu# Enable workarounds for selected Cortex-A53 erratas. 53*91f16700SchasingluluA53_DISABLE_NON_TEMPORAL_HINT := 1 54*91f16700SchasingluluERRATA_A53_826319 := 1 55*91f16700SchasingluluERRATA_A53_836870 := 1 56*91f16700SchasingluluERRATA_A53_855873 := 1 57*91f16700Schasinglulu 58*91f16700Schasinglulu# Skip L1 $ flush when powering down Cortex-A57 CPUs 59*91f16700SchasingluluSKIP_A57_L1_FLUSH_PWR_DWN := 1 60*91f16700Schasinglulu 61*91f16700Schasinglulu# Enable higher performance Non-cacheable load forwarding 62*91f16700SchasingluluA57_ENABLE_NONCACHEABLE_LOAD_FWD := 1 63