1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <pmc.h> 11*91f16700Schasinglulu #include <tegra_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define SB_CSR 0x0 14*91f16700Schasinglulu #define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* CPU reset vector */ 17*91f16700Schasinglulu #define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ 18*91f16700Schasinglulu #define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ 19*91f16700Schasinglulu 20*91f16700Schasinglulu extern void tegra_secure_entrypoint(void); 21*91f16700Schasinglulu 22*91f16700Schasinglulu /******************************************************************************* 23*91f16700Schasinglulu * Setup secondary CPU vectors 24*91f16700Schasinglulu ******************************************************************************/ 25*91f16700Schasinglulu void plat_secondary_setup(void) 26*91f16700Schasinglulu { 27*91f16700Schasinglulu uint32_t val; 28*91f16700Schasinglulu uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; 29*91f16700Schasinglulu 30*91f16700Schasinglulu INFO("Setting up secondary CPU boot\n"); 31*91f16700Schasinglulu 32*91f16700Schasinglulu /* setup secondary CPU vector */ 33*91f16700Schasinglulu mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, 34*91f16700Schasinglulu (reset_addr & 0xFFFFFFFF) | 1); 35*91f16700Schasinglulu val = reset_addr >> 32; 36*91f16700Schasinglulu mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* configure PMC */ 39*91f16700Schasinglulu tegra_pmc_cpu_setup(reset_addr); 40*91f16700Schasinglulu tegra_pmc_lock_cpu_vectors(); 41*91f16700Schasinglulu } 42