1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu 7*91f16700Schasingluluinclude common/fdt_wrappers.mk 8*91f16700Schasinglulu 9*91f16700SchasingluluARM_ARCH_MAJOR := 8 10*91f16700SchasingluluARM_ARCH_MINOR := 2 11*91f16700Schasinglulu 12*91f16700Schasinglulu# platform configs 13*91f16700SchasingluluENABLE_CONSOLE_SPE := 1 14*91f16700Schasinglulu$(eval $(call add_define,ENABLE_CONSOLE_SPE)) 15*91f16700Schasinglulu 16*91f16700SchasingluluENABLE_STRICT_CHECKING_MODE := 1 17*91f16700Schasinglulu$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE)) 18*91f16700Schasinglulu 19*91f16700SchasingluluUSE_GPC_DMA := 1 20*91f16700Schasinglulu$(eval $(call add_define,USE_GPC_DMA)) 21*91f16700Schasinglulu 22*91f16700SchasingluluRESET_TO_BL31 := 1 23*91f16700Schasinglulu 24*91f16700SchasingluluPROGRAMMABLE_RESET_ADDRESS := 1 25*91f16700Schasinglulu 26*91f16700SchasingluluCOLD_BOOT_SINGLE_CPU := 1 27*91f16700Schasinglulu 28*91f16700Schasinglulu# platform settings 29*91f16700SchasingluluTZDRAM_BASE := 0x40000000 30*91f16700Schasinglulu$(eval $(call add_define,TZDRAM_BASE)) 31*91f16700Schasinglulu 32*91f16700SchasingluluMAX_XLAT_TABLES := 25 33*91f16700Schasinglulu$(eval $(call add_define,MAX_XLAT_TABLES)) 34*91f16700Schasinglulu 35*91f16700SchasingluluMAX_MMAP_REGIONS := 30 36*91f16700Schasinglulu$(eval $(call add_define,MAX_MMAP_REGIONS)) 37*91f16700Schasinglulu 38*91f16700Schasinglulu# enable RAS handling 39*91f16700SchasingluluHANDLE_EA_EL3_FIRST_NS := 1 40*91f16700SchasingluluENABLE_FEAT_RAS := 1 41*91f16700Schasinglulu 42*91f16700Schasinglulu# platform files 43*91f16700SchasingluluPLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \ 44*91f16700Schasinglulu -I${SOC_DIR}/drivers/include 45*91f16700Schasinglulu 46*91f16700SchasingluluBL31_SOURCES += ${TEGRA_GICv2_SOURCES} \ 47*91f16700Schasinglulu drivers/ti/uart/aarch64/16550_console.S \ 48*91f16700Schasinglulu lib/cpus/aarch64/denver.S \ 49*91f16700Schasinglulu ${TEGRA_DRIVERS}/bpmp_ipc/intf.c \ 50*91f16700Schasinglulu ${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \ 51*91f16700Schasinglulu ${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \ 52*91f16700Schasinglulu ${TEGRA_DRIVERS}/smmu/smmu.c \ 53*91f16700Schasinglulu ${SOC_DIR}/drivers/mce/mce.c \ 54*91f16700Schasinglulu ${SOC_DIR}/drivers/mce/nvg.c \ 55*91f16700Schasinglulu ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \ 56*91f16700Schasinglulu ${SOC_DIR}/drivers/se/se.c \ 57*91f16700Schasinglulu ${SOC_DIR}/plat_memctrl.c \ 58*91f16700Schasinglulu ${SOC_DIR}/plat_psci_handlers.c \ 59*91f16700Schasinglulu ${SOC_DIR}/plat_setup.c \ 60*91f16700Schasinglulu ${SOC_DIR}/plat_secondary.c \ 61*91f16700Schasinglulu ${SOC_DIR}/plat_sip_calls.c \ 62*91f16700Schasinglulu ${SOC_DIR}/plat_smmu.c \ 63*91f16700Schasinglulu ${SOC_DIR}/plat_trampoline.S 64*91f16700Schasinglulu 65*91f16700Schasingluluifeq (${USE_GPC_DMA}, 1) 66*91f16700SchasingluluBL31_SOURCES += ${TEGRA_DRIVERS}/gpcdma/gpcdma.c 67*91f16700Schasingluluendif 68*91f16700Schasinglulu 69*91f16700Schasingluluifeq (${ENABLE_CONSOLE_SPE},1) 70*91f16700SchasingluluBL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S 71*91f16700Schasingluluendif 72*91f16700Schasinglulu 73*91f16700Schasinglulu# RAS sources 74*91f16700Schasingluluifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1) 75*91f16700SchasingluluBL31_SOURCES += lib/extensions/ras/std_err_record.c \ 76*91f16700Schasinglulu lib/extensions/ras/ras_common.c \ 77*91f16700Schasinglulu ${SOC_DIR}/plat_ras.c 78*91f16700Schasingluluendif 79*91f16700Schasinglulu 80*91f16700Schasinglulu# SPM dispatcher 81*91f16700Schasingluluifeq (${SPD},spmd) 82*91f16700Schasingluluinclude lib/libfdt/libfdt.mk 83*91f16700Schasinglulu# sources to support spmd 84*91f16700SchasingluluBL31_SOURCES += plat/common/plat_spmd_manifest.c \ 85*91f16700Schasinglulu ${LIBFDT_SRCS} 86*91f16700Schasinglulu 87*91f16700SchasingluluBL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 88*91f16700Schasingluluendif 89