1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/bl_common.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <smmu.h> 10*91f16700Schasinglulu #include <tegra_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define BOARD_SYSTEM_FPGA_BASE U(1) 13*91f16700Schasinglulu #define BASE_CONFIG_SMMU_DEVICES U(2) 14*91f16700Schasinglulu #define MAX_NUM_SMMU_DEVICES U(3) 15*91f16700Schasinglulu 16*91f16700Schasinglulu static uint32_t tegra_misc_read_32(uint32_t off) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); 19*91f16700Schasinglulu } 20*91f16700Schasinglulu 21*91f16700Schasinglulu /******************************************************************************* 22*91f16700Schasinglulu * Handler to return the support SMMU devices number 23*91f16700Schasinglulu ******************************************************************************/ 24*91f16700Schasinglulu uint32_t plat_get_num_smmu_devices(void) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu uint32_t ret_num = MAX_NUM_SMMU_DEVICES; 27*91f16700Schasinglulu uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> 28*91f16700Schasinglulu BOARD_SHIFT_BITS) & BOARD_MASK_BITS); 29*91f16700Schasinglulu 30*91f16700Schasinglulu if (board_revid == BOARD_SYSTEM_FPGA_BASE) { 31*91f16700Schasinglulu ret_num = BASE_CONFIG_SMMU_DEVICES; 32*91f16700Schasinglulu } 33*91f16700Schasinglulu 34*91f16700Schasinglulu return ret_num; 35*91f16700Schasinglulu } 36